1. 1 EECS 373 Design of Microprocessor-Based Systems Mark Brehob University of Michigan Lecture 7: Finish interrupts, group talks, start on serial buses Sept 24 th 2013

2. Announcements Exam will be on Wednesday 10/16 from 7-9pm. –If you have a class conflict, let me know in the next 48 hours. –Again, sorry it couldn’t be held during class time, but the College said there was no space to hold it in. HW3 will be posted later today –(Actually posted on Sunday) Discuss Lab schedule 2

3. High-level review of interrupts Why do we need them? Why are the alternatives unacceptable? –Convince me! What sources of interrupts are there? –Hardware and software! What makes them difficult to deal with? –Interrupt controllers are complex: there is a lot to do! Enable/disable, prioritize, allow premption (nested interrupts), etc. –Softare issues non-trivial Can’t trash work of task you interrupted Need to be able to restore state Shared data issues are a real pain 3

4. ARM interrupt review 1.we’ve got a bunch of memory-mapped registers that control things ( NVIC ) –Enable/disable individual interrupts –Set/clear pending –Interrupt priority and preemption 2.We’ve got to understand how the hardware interrupt lines interact with the NVIC 3.And how we figure out where to set the PC to point to for a given interrupt source. 4

5. 1. NVIC registers (example) 5

6. 1. More registers (example) 6

7. 1. Yet another part of the NVIC registers! 7

8. 2. How external lines interact with the NVIC 8 The normal case. Once Interrupt request is seen, processor puts it in “pending” state even if hardware drops the request. IPS is cleared by the hardware once we jump to the ISR. This figure and those following are from The Definitive Guide to the ARM Cortex-M3, Section 7.4

9. 3. How the hardware figures out what to set the PC to g_pfnVectors:.word _estack.word Reset_Handler.word NMI_Handler.word HardFault_Handler.word MemManage_Handler.word BusFault_Handler.word UsageFault_Handler.word 0.word SVC_Handler.word DebugMon_Handler.word 0.word PendSV_Handler.word SysTick_Handler.word WdogWakeup_IRQHandler.word BrownOut_1_5V_IRQHandler.word BrownOut_3_3V_IRQHandler.............. (they continue) 9

10. 10

11. What happens to architected state on an interrupt? 11

12. So let’s say a GPIO pin goes high - When will we get an interrupt? - What happens if the interrupt is allowed to proceed? 12

13. What happens when we return from an ISR? 13

14. Other stuff: The xPSR register layout 14

15. Example of Complexity: The Reset Interrupt 1)No power 2)System is held in RESET as long as VCC15 < 0.8V a)In reset: registers forced to default b) RC-Osc begins to oscillate c)MSS_CCC drives RC-Osc/4 into FCLK d)PORESET_N is held low 3)Once VCC15GOOD, PORESET_N goes high a)MSS reads from eNVM address 0x0 and 0x4 15

16. Group talks in EECS 373 16

17. Talk about talks Groups of 2-3 folks –Not your lab partner 12 minutes for the talk, ~3 minutes for questions Four parts –Meet with me about 2-3 weeks ahead of time to discuss topic idea. –Give first practice talk about 1-2 weeks before scheduled date (10%) –Second practice talk a few days before scheduled date (10%) –Give talk in class (80%) 17

18. Topic talk (continued) Each talk must include –An explanation of how the topic relates to embedded systems –An understanding of high-level issues including tradeoffs Need to produce at least one original graph explaining tradeoffs. –Some detailed explanation of a relevant part of the topic –Where others can go to learn more information We’ll take 10 minutes at the end of class to form groups of 2-3. –By 9pm groups should fill out form at http://tinyurl.com/373TTF13 If you don’t have a group by that time, send me an e-mail and I’ll form them. http://tinyurl.com/373TTF13 18

19. Serial Buses Some generic information UART (I2C and SPI next time) 19

20. Fun with buses A multidrop bus (MDB) is a computer bus in which all components are connected to the same set of electrical wires. (from Wikipedia) –In the general case, a bus may have more than one device capable of driving it. That is, it may be a “multi-master” bas as discussed earlier.

21. How can we handle multiple (potential) bus drivers? (1/3) Tri-state devices, just have one device drive at a time. Everyone can read though –Pros: Very common, fairly fast, pin- efficient. –Cons: Tri-state devices can be slow. –Especially drive-to-tristate? Need to be sure two folks not driving at the same time –Let out the magic smoke. –Most common solution (at least historically) Ethernet, PCI, etc.

22. How can we handle multiple (potential) bus drivers? (2/3) MUX –Just have each device generate its data, and have a MUX select. That’s a LOT of pins. –Consider a 32-bit bus with 6 potential drivers. »Draw the figure. »How many pins needed for the MUX? –Not generally realistic for an “on-PCB” design as we’ll need an extra device (or a lot of pins on one device) But reasonable on-chip –In fact AHB, APB do this.

23. How can we handle multiple (potential) bus drivers? (3/3) “pull-up” aka “open collector” aka “wired AND” –Wire is pulled high by a resistor –If any device pulls the wire low, it goes low. Pros: –If two devices both drive the bus, it still works! Cons: –Rise-time is very slow. –Constant power drain. Pros: –If two devices both drive the bus, it still works! Cons: –Rise-time is very slow. –Constant power drain. Sees use in I2C, CAN.

24. External memory attaches to the processor via the external memory controller and bus 24 Atmel SAM3U

25. UART Universal Asynchronous Receiver/Transmitter –a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. –UARTs are commonly used in conjunction with communication standards such as EIA, RS-232, RS-422 or RS- 485. –The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such as differential signaling etc.) typically are handled by a special driver circuit external to the UART. 25 Most of the UART stuff (including images) Taken from Wikipedia!

26. Protocol Each character is sent as –a logic low start bit –a configurable number of data bits (usually 7 or 8, sometimes 5) –an optional parity bit –one or more logic high stop bits. 26

27. Variations and fun times UART is actually a generic term that includes a large number of different devices/standards. –RS-232 is a standard that specifies “electrical characteristics and timing of signals, the meaning of signals, and the physical size and pin out of connectors. 27

28. Signals (only most common) The RXD signal of a UART is the signal receiving the data. This will be an input and is usually connected to the TXD line of the downstream device. The TXD signal of a UART is the signal transmitting the data. This will be an output and is usually connected to the RXD line of the downstream device. The RTS# (Ready to Send) signal of a UART is used to indicate to the downstream device that the device is ready to receive data. This will be an output and is usually connected to the CTS# line of the downstream device. The CTS# (Clear to Send) signal of a UART is used by the downstream device to identify that it is OK to transmit data to the upsteam device. This will be an input and is usually connected to the RTS# line of the upstream device. 28

29. 29 DB9 stuff DTE vs DCE Pinout of a DCE? Common ground? Noise effects? Wiring a DTE device to a DCE device for communication is easy. The pins are a one-to-one connection, meaning all wires go from pin x to pin x. A straight through cable is commonly used for this application. In contrast, wiring two DTE devices together requires crossing the transmit and receive wires. This cable is known as a null modem or crossover cable.

30. 30 RS-232 transmission example

31. Key observations No shared clock! Lots of overhead Quite complex No shared clock! 31