Presentation is loading. Please wait.

Presentation is loading. Please wait.

CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC prototyping service at CMP Kholdoun TORKI CMP 46,

Published byEverett Day Modified over 9 years ago

Similar presentations

Presentation on theme: "CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC prototyping service at CMP Kholdoun TORKI CMP 46,"— Presentation transcript:

1 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC prototyping service at CMP Kholdoun TORKI Kholdoun.Torki@imag.fr CMP 46, Avenue Félix Viallet, 38031 Grenoble, France http://cmp.imag.fr

2 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Agenda Introduction Collaboration for 3D-IC MPW runs service Tezzaron Process overview 3D-IC Design Platform TSV and wafer stacking from austriamicrosystems Conclusion

3 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo  CMP created in 1981  Offering industrial quality process lines (University process lines cannot offer a stable yield)  Design-kits to link CAD and MPW, to facilitate the design.  Customer base development + Universities / Research Labs + Industry + 1000 Institutions in 70 countries  Non-profit, Non-sponsored Introduction

4 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Multi-Project Wafer runs allow to share the price by sharing the reticle area. r Prototype fabrication. r Low volume productions (some hundreds to hundred thousands parts) Prototypes Low volume production Shared cost wafer Multi-Project Wafer (MPW)

5 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo IC : austriamicrosystems STMicroelectronics 28nm/32nm CMOS 40nm CMOS 7LM 65nm CMOS 7LM 130nm CMOS 6LM 65nm SOI 130nm SOI 130nm SiGe BiCMOS 0.35 µ CMOS / CMOS-Opto 0.35 µ SiGe 0.35 µ HV CMOS 0.35 µ HV CMOS EEPROM 0.18 µ CMOS 0.18 µ HV CMOS MEMS : CMP/austriamicrosystems MEMSCAP 0.35 µ CMOS bulk micromachining PolyMUMPSMetalMUMPSSOI-MUMPS 3D-IC : Tezzaron / GlobalFoundries 2 Tiers 3D-IC / 130nm CMOS TriQuint Semiconductor 0.15 µ GaAs D-mode pHEMPT TowerJazz 0.18 µ CMOS Technology Process Portfolio in 2011

6 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo CMC-CMP-MOSIS Collaboration

7 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Stimulate the activity by sharing the expenses for manufacturing. Join forces for the technical support, and dedicate roles for each partner. Make easier the tech support for local users respectively by each local center. Because there is no standard for the 3D-IC integration, it is urgent to setup an infrastructure making possible a broad adoption of 3D-ICs. That will have a beneficial effect on prices, more frequent MPW runs, and more skilled engineers. Benefits for a global Infrastructure CMC / CMP / MOSIS partnering for 3D-IC process access

8 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo CMC-CMP-MOSIS partnering on 3D-IC CMP/CMC/MOSIS partner to introduce a 3D-IC process Grenoble, France, 22 June 2010, CMP/CMC/MOSIS are partnering to offer a 3D-IC MPW service based on Tezzaron’s SuperContact technology and GLOBALFOUNDRIES 130nm CMOS. The first MPW run is scheduled to 31 May 2011: - 2-tier face-to-face bonded wafers - 130nm CMOS process for both tiers - Top tier exposing TSV and backside metal pads for wire bonding. A design-kit supporting 3D-IC design with standard-cells and IO libraries is available. Further MPW runs will be scheduled supporting process flavors (multiple tiers beyond 2, different CMOS flavors for different tiers,...) driven by user requirements. Potential users are encouraged to contact CMP for details : cmp@imag.fr

9 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo CMC - CMP - MOSIS Cooperation CMC supporting Canadian Customers CMP supporting European Customers MOSIS supporting US Customers

10 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Tezzaron 2-Tier Process (130nm CMOS) Process Overview

11 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Source Yole Development

12 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Tezzaron Process Flow for TSV and DBI (using Via Middle process) Starting wafer in 130nm (5 Cu metal layers + 6 th Cu metal as DBI) Source Tezzaron

13 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Tezzaron Process Flow for TSV and DBI (using Via Middle process) Cu

14 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Top Tier (10um thickness) Bottom Tier (Handle wafer) Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) DBIs continuing the stacking Source Tezzaron

15 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Top Tier (10um thickness) Bottom Tier (Handle wafer) Resulting 2-tier 3D-IC integration TSV and DBI (Via Middle Process) Bond pad for wire bonding or bump, flip-chip … Source Tezzaron

16 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC MPW runs

17 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC Potential Users HEP Labs 3D-IC MPW Initial Infrastructure First MPW Run organized by FermiLab using an Industrial Process Clustering Manufacturing

18 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Source FermiLab (3D Consortium Meeting) MPW Full Frame Notice Symmetry about vertical center line Test chips: TX, TY 2.0 x 6.3 mm Top tiersBottom Tiers Subreticules: A, B, C, D, E, F, G, H, I, J 5.5 x 6.3 mm 3D Consortium : 1st MPW run

19 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC Users 3D-IC MPW Infrastructure CMC-CMP-MOSIS partnering to offer 3D-IC MPW runs Clustering Manufacturing Critical mass allow frequent MPW runs and low pricing In discussion In place

20 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo CMP/MOSIS/CMC : 1st MPW run Deadline originally planned for May 31 st, 2011

21 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC Design Platform

22 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Tezzaron / GlobalFoundries Design Platform The Design Platform is modular. It has all features for full-custom design or semi-custom automatic generation design. PDK : Original PDK from GF + (TSV / DBI) definition from Tezzaron Libraries : CORE and IO standard libraries from ARM Memory compilers : SPRAM, DPRAM and ROM from ARM 3D-IC Utilities : Contributions developments embedded in the platform Tutorials, User’s setup. All modules inside the platform refer to a unique variable, making it portable to any site. The installation procedure is straightforward. Support of CDB and OpenAccess databases.

23 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo  DBI (direct bonding interface) cells library. (FermiLab)  3D Pad template compatible with the ARM IO lib. (IPHC)  Preprocessor for 3D LVS / Calibre (NCSU)  Skill program to generate an array of labels (IPHC)  Calibre 3D DRC (Univ. of Bonn)  Dummies filling generator under Assura (CMP)  Basic logic cells and IO pads (FermiLab)  Floor-planning / automatic Place & Route using DBIs, and TSVs (CMP)  Skill program generating automatically sealrings and scribes (FermiLab)  MicroMagic PDK (Tezzaron/NCSU) Collaborative Work to the Design Platform HEP labs contributing with Programs, Libraries, and Utilities. All included in the Design Platform

24 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Virtuoso Layout Editor with 3D layers and verification TSV Back Metal Back Pad DBI Assura Calibre Virtuoso from Cadence

25 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo True 3D Mask Layout Editor MicroMagic MAX-3D Technology Files fully supported by Tezzaron

26 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo - DBIs Placement - TSVs Placement - Obstructions on TSVs - Std cells Placement - Clock Tree Synthesis Filler Cells Placement - Clock routing - Final routing Automatic P & R Design Flow (From Floor-Plan to Routed Design)

27 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo assura calibre cds_cdb cds_oa doc eldo hercules hspice prep3DLVS skill spectre strmMaptables_ARM strmMaptables_Encounter chrt13lprf_DK009_Rev_1D (Version issued in Q1 2011) calibre: 3DDRC 3DLVS DRC FILLDRC calibreSwitchDef assura: FILLDRC LVS QRC hercules: DRC LVS STAR_RCXT PDK Tezzaron / GlobalFoundries

28 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Access to the Design-Rules and the Design Platform Customer Request Signed NDA reception NDA http://cmp.imag.fr Foundry’s Agreement Yes Design kit & Design Rules access NDA Edition Request to access from CMP Web page or by E-mail to : cmp@imag.fr The user receive by E-mail the NDA + ARM lirary Addendum. The user sign and return by post 2 original signed copies CMP forward to Tezzaron the NDAs. When Tezzaron is OK, they counter-sign and return one copy to CMP. CMP return the copy to the user and give the access to the DRM and Design-Platform.

29 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo CPPM, Marseille, France IPHC, Strasbourg, France LAL, Orsay, France LPNHE, Paris, France IRFU, CEA Saclay, France LAPP, Annecy-Le-Vieux, France ENSTA PARISTECH, Paris, France ISEA, Toulouse, France ENSSAT – Universite Rennes, France CEA-DIF, France University of Bergamo, Italy University of Bologna, Italy University of Perugia, Italy INFN, Roma, Italy INFN, Pavia, Italy INFN, Pisa, Italy University of Bonn, Germany University of Barcelona, Spain IMSE-CNM-CSIC, Sevilla, Spain TuDelft, The Netherlands University of Turku, Finland Norwegian University, Trondheim, Norway 22 Users in Europe Tezzaron Semiconductor, USA FermiLab, USA North Carolina State University, USA MOSIS, USA CMC Microsystems, Canada University of Sherbrooke, Canada + Other centers supported by MOSIS and CMC Not listed here. Users having access to the Design Platform

30 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 100µ TSV on 0.35µ CMOS from Austriamicrosystems

31 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo

32 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo

33 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo

34 CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo Conclusion  CMC-CMP-MOSIS collaboration to offer services for 3D-IC prototyping and low volume productions.  Continuous enhancements on the Design Platform offering updates, features, and design methodologies.  First MPW run deadline : May 31 st, 2011

Download ppt "CNRS – INPG – UJF AIDA WP3 3D Industry Workshop, May 23 rd, 2011, Bergamo 3D-IC prototyping service at CMP Kholdoun TORKI CMP 46,"

Similar presentations

Tezzaron Semiconductor 06/14/2011 3D_IC for Real Chips Bob Patti, CTO 1.

Tezzaron Semiconductor 06/14/2011 3D_IC for Real Chips Bob Patti, CTO 1.
Tezzaron Semiconductor 04/08/2013 1 Implementing 2.5D and 3D Devices Bob Patti, CTO

Tezzaron Semiconductor 04/08/ Implementing 2.5D and 3D Devices Bob Patti, CTO
Commercial-Foundry Flexible Mixed Signal ASIC Design Center ACME SSED Foundry-Portable, Mixed-Signal ASIC Design Center A pplication of C ommercially M.

Commercial-Foundry Flexible Mixed Signal ASIC Design Center ACME SSED Foundry-Portable, Mixed-Signal ASIC Design Center A pplication of C ommercially M.
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim

Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim
MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.

MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.
USC INFORMATION SCIENCES INSTITUTE MOSIS OVERVIEW MSE99 July 19, 1999 César A. Piña

USC INFORMATION SCIENCES INSTITUTE MOSIS OVERVIEW MSE99 July 19, 1999 César A. Piña
Microelectronics User Group Meeting TWEPP 2012, Oxford, UK 19/9/2012.

Microelectronics User Group Meeting TWEPP 2012, Oxford, UK 19/9/2012.
Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,

Design Tools, Flows and Library Aspects during the FE-I4 Implementation on Silicon Vladimir Zivkovic National Institute for Subatomic Physics Amsterdam,
Status of 65nm foundry access for Aida June 2013 A. Marchioro CERN/PH-ESE.

Status of 65nm foundry access for Aida June 2013 A. Marchioro CERN/PH-ESE.
65nm CMOS Foundry Services

65nm CMOS Foundry Services
CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy CAD Tools for 3D-IC and TSV-based designs Kholdoun TORKI

CNRS – INPG – UJF AIDA Workshop, April 8-9, 2013, Frascati (Roma), Italy CAD Tools for 3D-IC and TSV-based designs Kholdoun TORKI
MultiMEMS MPW Design Introduction Course Part1: Introduction.

MultiMEMS MPW Design Introduction Course Part1: Introduction.
Status and outlook of the Medipix3 TSV project

Status and outlook of the Medipix3 TSV project
Hans-Günther Moser MPI für Physik TIPP 2011 Satellite Meeting on 3D Integration June 14, 2011 3D Technology Developments in Europe and EU Supported Activities.

Hans-Günther Moser MPI für Physik TIPP 2011 Satellite Meeting on 3D Integration June 14, D Technology Developments in Europe and EU Supported Activities.
3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.

3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.
R. Kluit Electronics Department Nikhef, Amsterdam. Integrated Circuit Design.

R. Kluit Electronics Department Nikhef, Amsterdam. Integrated Circuit Design.
High-Quality, Low-Cost IC Fabrication with MOSIS

High-Quality, Low-Cost IC Fabrication with MOSIS
3D Integration activities AIDA WP3 Frascati 2013 Abdenour LOUNIS, AIDA Frascati 2013 Abdenour LOUNIS, G. Martin Chassard, Damien Thienpont, Jeanne Tong-Bong.

3D Integration activities AIDA WP3 Frascati 2013 Abdenour LOUNIS, AIDA Frascati 2013 Abdenour LOUNIS, G. Martin Chassard, Damien Thienpont, Jeanne Tong-Bong.
3D Vertex Detector Status The requirement for complex functionality in a small pixel led us to investigate vertically integrated (3D) processes. Developed.

3D Vertex Detector Status The requirement for complex functionality in a small pixel led us to investigate vertically integrated (3D) processes. Developed.
Fabian Hügging – University of Bonn – February - 16 - 20111 WP3: Post processing and 3D Interconnection M. Barbero, L. Gonella, F. Hügging, H. Krüger and.

Fabian Hügging – University of Bonn – February WP3: Post processing and 3D Interconnection M. Barbero, L. Gonella, F. Hügging, H. Krüger and.

Similar presentations

Ads by Google