1. Presenter : Shao-Cheih Hou Sight count : 11 ASPDAC ‘08

2. Existing SoC debug techniques mainly target bus- based systems. They are not readily applicable to the emerging system that use Networkon-Chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and timestamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores’ debug processes. Experimental results show the functionalities of the proposed DP and its area overhead1.

3. More and more IP connect on bus in SoC  Single bus is not efficiency  Full connect is too complex and high cost  Network is a good way for chip(NoC) In NoC, too many IPs need to verification  Design for debug => debug platform  Debug need more flexible 。 Programmable trigger 。 Trace (timestamping) 。 Delay control 。 Run stop 。 Debug prob

4. This paper Silicon debug platform Debug method interface Coresight[4] DfD for embedded cores[4] Open Core peotocol[15] Tracing[1,3, 12,13,22] JTAG[21] Internal nodes[21] Monitor for NoC[7,8]

5. Debug software  Software control  Each core structure config  Driver match Off-chip debug controller  OCP and JTAG interface  Command I/O  Data output On-chip debug architecture  DA(debug agent)  DP(debug probe)

6. 6 DA (Debug Agent) Receive/send debug command/data from/to Off-chip Debug Controller by using system JTAG port Change debug command to package form, and passing to specific CUD or DP Receive package form network and change to debug data

8. Connect to Network interface(NI)  OCP protocol (slave interface)  Memory-map for each DP Control the delay of the debug probe  For data synchronize

9. JTAG Interface  Another way to configure the delay control ARM ICE JTAG protocol use in this paper

11. Trigger Unit  Control for config  Detector as comparator  MUX for output record Trace Unit  Trace after trigger  Shadow buffer for start cycle  Record package Record format

12. The method for DP setup and run

13. Environment setup  ARM EICE JTAG  OCP protocol Function Test – delay R/W

14. Function Test – Transaction operation Area of DP

15. The paper propose a debug platform  For complex NoC base  Bus config and JTAG parallel  Trace for both core information and protocol information  Reconfigurable HW

16. Similar as problem in my target  NoC(not bus system) debug  Memory interface signal trace  JTAG and interconnect debug parallel Problem for this paper  Only the simulation, no real case  Area analyze only for DP, not all the platform  No detail for SW and off-chip debug controller