1. A 10 bit,100 MHz CMOS Analog- to-Digital Converter

2. Outline zIntroduction zHigh Speed A/D Converter Architectures zProposed A/D Converter Architecture zCircuit Design and Simulations zPrototype Chip Test Results zConclusion zResearch Plan

3. Applications of High Speed High Resolution A/D Converter zHigh frequency digital data communication zWaveform acquisition instruments zMedical Imaging zVideo Signal Processing

4. Increasing DSP complexity in communications systems

5. High Resolution High Speed CMOS A/D Converters

6. Fully Parallel(Flash) A/D Converter zConceptually most straightforward 1. Highest possible speed 2. Resolution: 8-10bits zDisadvantages 1. 2 comparators requires So, Hardware complexity grows exponentially with resolution 2. Large power dissipation and input capacitance

7. Two-Step A/D Converter zLess hardware complexity than Flash type zDigital error correction is possible zDisadvantages: y Requires inter-stage amplifier (longer conversion time) y Requires multiple clocks per conversion

8. Multi-Stage Pipeline A/D Converter zWell-suited to CMOS, as residue amplifier has built-in S/H zMay repeat same blocks in cascade zApproximately linear hardware cost with resolution zLimitations: 1. Residue amplifier settling is speed bottleneck 2. Linearity determined by input S/H and residue formation

9. Parallel Pipelined A/D Converter zConversion rate increases with the number of channels zInput S/H must acquire singal at full Nyquist bandwidth zPerformance ultimately limited by: 1. Timing skews and jitter between channels 2. Mismatch in gain, offset and full scale between channels

10. Effect of Sampling Timing Offset in Parallel Pipelined A/D Converter

11. SNR with gain mismatch 2 channel pipeline ADC

12. Design Specification z10 bit resolution z100 MHz conversion rate zFully Differential Implementation z  1.0V input full scale z1.0  m n-well CMOS technology with linear capacitance option z1.0 W power dissipation z2-channel 3-stage pipelined architecture z4 bit/stage conversion zParallel Pipeline Switch Cap. Residue Amplifier zResistor Ladder DAC zOn-chip clock buffer

13. Detail Block Diagram of Architecture

14. Timing Diagram of S/H, 4-bit ADDA, and RA

15. Schematic of Non-resetting S/H zEquivalent to two resetting S/H zFollowing stage can obtain the valid data for full period(10ns) zDisadvantage: yCh and Cd increase a time constant

16. Simulated Dynamic Performance of S/H

17. 4-bit AD-DA Block Diagram

18. Residue Amplifier zGain of 2 Residue Amplifier: yGenerate a residue (subtract DAC output from S/H output) yReduce inter-channel offect  Offset Cancellation Scheme zGain of 4 Residue Amplifier: yReduce inter-channel offset  Offset Cancellation Scheme yCompensation capacitor added ot stabilized loop when sampling

19. Digital Circuit in ADC

20. Clock Generation Circuit

21. Measured SNDR,THD,and SFDR at 500 KHz input

22. Measured Signal / (Noise+Distortion) at 4, 50 & 95 MHz Sampling rate

23. Power Dissipation zTotal power dissipation = 1.1W @ 95MS/s

24. Floor Plan of A/D Converter zLayout Design Issues: yClock distribution yReduce the Offset in Residue Amplifier

25. Summary of A/D Characteristics

26. Conclusions z10-bit resolution z95MS/s conversion rate z1  m n-well CMOS technology with linear capacitor option zSpurious tones are less -65db after simple on chip offset cancellation z1.2W power dissipation @ single 5V zDigital error correction zFirst 10-bit, 100MS/s CMOS ADC

27. Research Plan zInvestigate further effects of architecture on SFDR zHope to design 14bit linear input S/H capable of 2.5MHz or higher clock rate zConsiderations: yNonlinearity in interstage of ADC (For example: Offset, Gain, Carpacitor and Resistor mismatch, Timing mismatch..)