1. More Examples Dataflow/Behavioral Modeling Section 4.12

2. Schedule 143/3MondayMore example of data flow versus behavior. 153/5WednesdayTest 1 L3/6ThursdayRandom number generator, mixed signal scope 163/10MondayLatches (1) 173/12WednesdayFlip-flops, L3/13ThursdayFlip-flops, D-latch, N/A3/17MondaySpring break N/A3/19WednesdaySpring break N/A3/20ThursdaySpring break 183/24MondayAnalysis of clocked sequential circuit (1), 193/26WednesdayAnalysis of clocked sequential circuit (2) L3/27ThursdayClocked sequential circuit Assign course project: hamming decoder.

3. Homework Hw2, hw2 & labs have been graded. Preview the lecture materials before the lab.

4. Verilog Modeling Verilog Modeling Styles – Gate-Level Modeling – Dataflow Modeling – Behavioral Modeling

5. Data Flow Modeling Data flow modeling of a combinational logic uses a number of operators that act on operands to produce desired results. The keyword assign is used frequently in the dataflow modeling.

6. Behavior Modeling Behavioral modeling represents the digital circuits at a functional and algorithmic level. It is used mostly to describe sequential circuits, but can also be used to describe combinational circuits. Behavioral description use the keyword always. The event control expression Specifies when the statements will execute. The target output statement must be of reg data type.

7. More Examples of Dataflow

8. Verilog HDL Operators A and B are both 4-bit binary numbers. A_gt_B is a logic 1 if A is greater than B. A_lt_B is a logic 1 if A is less than B. A_eq_B is a logic 1 if A is equal to B. A==B is not the same as A=B.

9. Partial Test Bench for mag_compare.v Use concatenation to form a 4-bit array called B.

10. Output

11. Four-Bit Adder Example {C4,S0, S1, S2, S3)=5-bit binary number {A0, A1, A2, A3)=4-bit binary number {B0, B1, B2, B3)=4-bit binary number C0 is a 1-bit binary number

12. Four-Bit Adder Output

13. More Examples of Behavioral Modeling

14. 4-to-1 MUX

15. 8-to-1 Mux if and else example

16. 8-to-1 MUX