1. 3D RGB LED Cube Group 15 Luke Ausley BSEE Joshua Moyerman BSPE Andrew Smith BSPE Sponsored by Stellascapes 1

2. Motivations and Goals Desire to discover innovative methods for improving LED cube design Project aligned with individual group member’s expertise and interest Diverse design aspects 2

3. Specifications TitleQTYUnits Cube Resolution10 x 10 x 10Voxels LED Lattice Dimensions50 x 50 x 50cm Outer Dimensions60 x 60 x 70cm Pitch5cm Refresh Rate100hz Animation Rate25fps Color Space24bit Operating Voltage120V Operating Current1A 3

4. High Level Diagram 4

5. High Level Work Distribution 5

6. Hardware Block Diagram 6

7. Key Hardware Design Decisions Multiplexing Control Hardware Structure o Joint FPGA/MCU LED Driver Board o TI LED Drivers o MOSFETs PCB Layout o Three separate two-layer PCBs 7

8. Driver Design Two identical driver boards will be used to reduce power dissipation and circuit board size and isolate faults. TLC5948A LED Drivers SI4101DY-T1-GE3 P Channel Mosfet Individually fused planes 8

9. Driver Schematic 9

10. Driver PCB Layout 10

11. Control Design FPGA and MCU based control system FPGA to handle interfacing to driver circuitry due to timing constraints MCU to handle user interfacing via ethernet FPGA and MCU will work together to complete the task of driving LEDs 11

12. FPGA and MCU Choice PIC24HJ265GP206A Microcontroller o Low cost, 16 bit architecture o Stellascapes existing experience with Microchip line of products o Readily available ethernet interface with TCP/IP Stack Xilinx XC3S200AVQ100 Spartan 3A FPGA o Team’s familiarity with Xilinx ISE from Digital Systems Lab work o Stellascapes interest in integrating FPGA with PIC24 12

13. Control Schematic 13

14. Control PCB Layout 14

15. PCBs Interfaced 15

16. Firmware - MCU Developed using C (6000 lines of code) Microchip MPLAB X IDE Microchip XC C Compiler Microchip’s freely available TCP/IP Stack 16

17. Firmware - FPGA Written in Verilog (1600 lines of code) Xilinx ISE 14.5 Development Environment Simulated using ISim 17

18. Firmware Update Cycle Updated FPGA code to be loaded via MCU Ethernet connection FPGA bitstream stored on 8Mb EEPROM MCU to control loading of FPGA Device 18

19. Power Supply Ablecom SP502-2S Output Voltage5 V Max Current30 A Input Voltage100-240 V Input Frequency50-60 Hz Max Input Current10 A Dimensions7x4x2 in 19

20. Construction 20

21. Construction 21

22. Prototype 22

23. Software 23

24. Software Design Choices Developed in Microsoft Visual Studio Environment (3200 lines of code) 24

25. Software Block Diagram 25

26. Animation Class Diagrams 26

27. LED Animation GUI 12 distinct animations 3 distinct color modes User Input HSV Scroll Random 24-bit color palette Brightness scaling 27

28. Communication E1.31 Streaming Architecture for Control Networks (sACN) Up to 512 color channels/packet Animation data sent over 6 packets 28

29. Simulators 29

30. Hardware Simulator Scrolling Text User Input Color Sine Ripple Random Color Rotating Sine HSV Scroll Color 30

31. Firmware Simulator 31

32. Budget ItemQtyTotal Cost LEDs1200$350 - Sponsored Construction MaterialsN/A$100 PCBs3$200 - Sponsored LED Drivers/MOSFETs20 ea$75 Power Supply1Group Owned Wire1200ft$100 Assorted ComponentsN/A$100 Estimated Overall Total$925 Estimated Amount Spent (Non-sponsored)$375 32

33. Challenges Production delays FPGA/Microprocessor interfacing 33

34. Successes All components operational in standalone Mature black-box software Timing specs met Proof of concept with moderate confidence Functional prototype 34

35. Special Thanks Stellascapes o Sponsorship 35

36. Questions? 36