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1 © Unitec New Zealand I2C Lecture 10 Date: - 2 Nov, 2011 Embedded Hardware ETEC 6416.

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Presentation on theme: "1 © Unitec New Zealand I2C Lecture 10 Date: - 2 Nov, 2011 Embedded Hardware ETEC 6416."— Presentation transcript:

1 1 © Unitec New Zealand I2C Lecture 10 Date: - 2 Nov, 2011 Embedded Hardware ETEC 6416

2 What is I2C I²C (Inter-Integrated Circuit, alternatively spelled I2C or IIC, most commonly pronounced I- squared-C) is a Master Slave invented by the Phillips semiconductor division, known today as NXP Semi- conductors, and is used for attaching low-speed peripherals to a computer or embedded system(micro- controller). 2 © Unitec New Zealand

3 The before mentioned reference design is a bus with a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes: master and slave: Master node — node that generates the clock and initiates communication with slaves Slave node — node that receives the clock and responds when addressed by the master 3 © Unitec New Zealand

4 Master and slave in the I 2 C bus The devices on the I 2 C bus are either masters or slaves. The master is always the device that drives the SCL clock line. The slaves are the devices that respond to the master. A slave cannot initiate a transfer over the I 2 C bus, only a master can do that. There can be, and usually are, multiple slaves on the I 2 C bus, however there is normally only one master at a time. 4 © Unitec New Zealand

5 When the master (a controller) wishes to talk to a slave (for example computer) it begins by issuing a start sequence on the I 2 C bus. A start sequence is one of two special sequences defined for the I 2 C bus, the other being the stop sequence. The start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change while the SCL (clock line) is high. When data is being transferred, SDA must remain stable and not change whilst SCL is high. The start and stop sequences mark the beginning and end of a transaction with the slave device. 5 © Unitec New Zealand

6 I 2 C bus communication pattern I 2 C bus uses start and stop bits to indicate the data starting and ending point. Address of slave is specified after start bit. A master can be a transmitter and a receiver depending on the R/W bit. If it is 0 then it is a transmitter and if 1 then a receiver. Data is always acknowledged by setting the SDA line to 0. Address can be 7 bits and 10 bits. 6 © Unitec New Zealand

7 Bus Communication System This is just two wires, that connect the different devices on the system. Both RS485 and I2C use this system. 7 © Unitec New Zealand


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