1. LAB 7: WDT+ and Low-Power Optimization
CS 4101 Introduction to Embedded Systems
LAB 7: WDT+ and Low-Power Optimization
Chung-Ta King
National Tsing Hua University

2. Introduction In this lab, we will learn WDT+ as the interval timer
Configuring the low-power mode of MSP430
CPU 擁有的五段省電模式、模組化的架構、彈性化的時脈系統

3. WatchDog Timer +

4. WDT+
Watchdog timer+ (WDT+) is a 16-bit timer that can be used as a watchdog or interval timer
Watchdog timer:
Performs a system restart after a software problem occurs, e.g., unintended infinite loop
Counts up and resets system when it reaches limit
The program must keep clearing the counter before the limit is reached to prevent a reset

5. Control of WDT+ Control register: WDTCTL
Password protected: to guard against accidental writes by requiring writing password WDTPW = 0x5A in upper byte  reset if password incorrect
But, reading WDTCTL returns 0x69 in upper byte
The lower byte of WDTCTL contains the bits that control the operation of the watchdog timer

6. WDT+ as Interval Timer Set WDTTMSEL bit in WDTCTL to 1
Set WDTSSEL bit in WDTCTL to select clock source: SMCLK or ACLK
Default clock is SMCLK derived from DCO at 1 MHz  default period is counts, or about 32 ms
Set WDTISx bits in WDTCTL to select interval
Clock source divided by 64, 512, 8192, or 32,768
Set WDTCNTCL bit in WDTCTL to clear counter

7. WDT+ Control Register

8. WDT+ Interrupt
WDT+ uses two bits in the Special Function Registers (SFRs) for interrupt control
WDT+ interrupt flag, WDTIFG, located in IFG1.0
WDT+ interrupt enable, WDTIE, located in IE1.0
WDTIFG is set when time interval expired
WDTIFG will request an interrupt if
WDTIE in IE1.0 and GIE in SR are enabled
WDTIFG can be automatically set/reset

10. Sample Code (MSP430G2xx1 _wdt_01)
Toggle P1.0 using interval from WDT+ at about 32ms based on default DCO/SMCLK
void main(void) {
WDTCTL = WDTPW+WDTTMSEL+WDTCNTCL; // Interval ~32ms
IE1 |= WDTIE; // Enable WDT interrupt
P1DIR |= 0x01; // Set P1.0 to output
_BIS_SR(LPM0_bits + GIE); // LPM0 w/ interrupt }
// Watchdog Timer interrupt service routine
#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer(void) {
P1OUT ^= 0x01; // Toggle P1.0

11. Low-Power Optimization

12. Low-Power Mode Mode CPU and Clocks Active
CPU active. All enabled clocks active
LPM0
CPU, MCLK disabled. SMCLK, ACLK active
LPM1
CPU, MCLK disabled. DCO disabled if not used for SMCLK. ACLK active
LPM2
CPU, MCLK, SMCLK, DCO disabled. ACLK active
LPM3
LPM4
CPU and all clocks disabled

13. Power Saving in MSP430
The most important factor for reducing power consumption is using the MSP430 clock system to maximize the time in LPM3
Low-power mode 2 or 3 is selected if bits CPUOff and SCG1 in the status register are set. Immediately after the bits are set, CPU, MCLK, and SMCLK operations halt and all internal bus activities stop until an interrupt request or reset occurs.
Peripherals that operate with the MCLK or SMCLK signal are inactive because the clock signals are inactive. Peripherals that operate with the ACLK signal are active or inactive according with the individual control registers and the module enable bits in the SFRs. All I/O port pins and the RAM/registers are unchanged. Wake up is possible byenabled interrupts coming from active peripherals or RST/NMI.
“Instant on” clock

14. Sample Code (MSP430G2xx1 _ta_01)
Toggle P1.0 using TA_0 every cycles
void main(void) {
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1DIR |= 0x01; // P1.0 output
CCTL0 = CCIE; // CCR0 interrupt enabled
CCR0 = 50000;
TACTL = TASSEL_2 + MC_2; // SMCLK, contmode
_BIS_SR(LPM0_bits + GIE); // LPM0 w/ interrupt }
#pragma vector=TIMERA0_VECTOR
__interrupt void Timer_A (void) {
P1OUT ^= 0x01; // Toggle P1.0
CCR0 += 50000; // Add Offset to CCR0
Use _BIC_SR_IRQ(LPM0_bits)
to exit LPM0

15. Basic Lab (This lab is an extension from Lab 4)
Flash green LED at 1 Hz using interrupt from Timer_A, driven by SMCLK sourced by VLO. While green LED flashing at 1 Hz, pushing the button flashes red LED at 2Hz and releasing the button turns off red LED. Use low-power mode as much as possible.
Hint: PORT1_VECTOR as interrupt type, WDT+ to control the flashing of red LED
Hint: Use P1IES to change the trigger mode (“High to Low” or “Low to High”)

16. P1IES
Timer_A, driven by SMCLK sourced by VLO.
BCSCTL3

17. Bonus
Flash green LED at 1 Hz using interrupt from Timer_A, driven by ACLK sourced by VLO in LPM3. While pushing the button, change from LPM3 to LPM0, stop flashing green LED, and flash red LED at 2 Hz using interrupt from Timer_A, driven by SMCLK sourced by VLO. Releasing the button returns the system to LPM3 and stops red LED flashing.