1. CPU Fetch/Execute Cycle
Computer program
Electronic clock
Computer Memory
Data/address buses
Fetch/Execute Cycle
Accumulator
ALU/Control Unit/Program Counter
CIR/MDR/MAR

2. Simple Microprocessor
Memory
Electronic Clock
Arithmetic Logic Unit
Accumulator
Control Unit
Memory Address Register
Current Instruction Register
Memory Data Register
Program Counter
Internal Bus
Special Internal Bus Structure
Data
Bus
Address Bus
Data bus

3. Simple Microprocessor
Memory
Simple Microprocessor 10
(2)
Electronic Clock 11
(3) 12
(R)
Internal Bus … PC
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
100
CIR
Special Internal Bus Structure
Bus
101
Data
102
MDR
Data bus
ALU
Bus

4. Simple Microprocessor
Memory
Simple Microprocessor 10
(2)
Electronic Clock 11
(3) 12
(R)
Internal Bus …
PC = 100
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
100
CIR
Special Internal Bus Structure
Bus
101
Data
102
MDR
Data bus
ALU
Bus

5. Fetch Phase (1st Instruction)
Memory
Fetch Phase (1st Instruction) 10
(2)
Electronic Clock 11
(3) 12
(R)
Internal Bus …
PC = 100
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
100
CIR
Special Internal Bus Structure
Bus
101
Data
102
MDR
Data bus
ALU
Bus

6. 1st Instruction Decoded
Memory
1st Instruction Decoded 10
(2)
Electronic Clock 11
(3)
Load number from memory location 10 12
(R)
Internal Bus …
PC = 101
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
CIR
Special Internal Bus Structure
Bus
101
Data
102
MDR
Data bus
ALU
Bus

7. 1st Instruction Executed
Memory
1st Instruction Executed 10
(2)
Electronic Clock 11
(3)
Load number from memory location 10 12
(R)
Internal Bus …
PC = 101
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
CIR
Special Internal Bus Structure
Bus
101
Data
102
MDR
Data bus
ALU
Bus

8. Fetch Phase (2nd Instruction)
Memory
Fetch Phase (2nd Instruction) 10
(2)
Electronic Clock 11
(3) 12
(R)
Internal Bus …
PC = 102
PC = 101
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
CIR
Special Internal Bus Structure
Bus
101
Data
102
MDR
Data bus
ALU
Bus

9. 2nd Instruction Decoded
Memory
2nd Instruction Decoded 10
(2)
Electronic Clock 11
(3)
Load number from memory location 11 12
(R)
Internal Bus …
PC = 102
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
CIR
Special Internal Bus Structure
Bus
Data
102
MDR
Data bus
ALU
Bus

10. 2nd Instruction Execution
Memory
2nd Instruction Execution 10
(2)
Electronic Clock 11
(3) 12
(R)
Internal Bus …
PC = 102
Data
Control Unit
Internal Bus
Bus
MAR
Address Bus
Data
Accumulator
Bus
Data
CIR
Special Internal Bus Structure
Bus
Data
102
MDR
Data bus
ALU +
Bus