1. ECE2030 Introduction to Computer Engineering Lecture 10: Building Blocks for Combinational Logic (1) Timing Diagram, Mux/DeMux Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2. 2 Combinational Logic Outputs, “at any time”, are determined by the input combination When input changed, output changed immediately –Real circuits is imperfect and have “propagation delay” A combinational circuit –Performs logic operations that can be specified by a set of Boolean expressions –Can be built hierarchically Combinational circuits N inputs M outputs

3. 3 Timing Diagram Describe the functionality of a logic circuit across time Represented by a waveform For combinational logic, Output is a function of inputs

4. 4 Timing Diagram of an AND Gate (Output=AB) Time A B Output (No Delay) t0t1t2t3t4t5t6t7t8t9t10t11t12 Note that the Output change can occur “at any Time” for Combinational logic

5. 5 Timing Diagram Example X Y Z F A B A B X Y Z F t0t1t2t3t4t5t6t7t8t9t10

6. 6 Timing Diagram Example X Y Z F A B A B F ABF 011 110 000 101 F = A  B t0t1t2t3t4t5t6t7t8t9t10

7. 7 Combinational Logic Outputs, “at any time”, are determined by the input combination We will discuss –Multiplexers / De-Multiplexers –Decoders / Encoders –Comparators –Parity Checkers / Generators –Binary Adders / Subtractors –Integer Multipliers Combinational circuits N inputs M outputs

8. 8 Multiplexers (Mux) Functionality: Selection of a particular input Route 1 of N inputs (A) to the output F Require selection bits (S) En(able) bit can disable the route and set F to 0 F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 En 4-to-1Mux

9. 9 Multiplexers (Mux) w/out Enable F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 4-to-1Mux S1S0A3A2A1A0F 00XXX00 01XX0X0 10X0XX0 110XXX0 00XXX11 01XX1X1 10X1XX1 111XXX1

10. 10 Multiplexers (Mux) w/out Enable S1S0F 00A0 01A1 10A2 11A3 F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 4-to-1Mux

11. 11 Logic Diagram of a 4-to-1 Mux S1 S0 A0 A1 A2 A3 F

12. 12 Multiplexers (Mux) w/ Enable EnS1S0F 0XX0 100A0 101A1 110A2 111A3 F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 En 4-to-1Mux

13. 13 4-to-1 Mux w/ Enable Logic S1 S0 A0 A1 A2 A3 F En

14. 14 4-to-1 Mux w/ Enable Logic S1 S0 A0 A1 A2 A3 F En Reduce one Gate Delay by using 4-input AND gate for the 2 nd level En

15. 15 4-to-1 Mux using Transmission Gates A0 A1 A2 A3 S0 S1 F S1S0F 00A0 01A1 10A2 11A3

16. 16 4-to-1 Mux using Transmission Gates A0 A1 A2 A3 S0=0 S1 F S1S0F 00A0 01A1 10A2 11A3 A0 A2

17. 17 4-to-1 Mux using Transmission Gates A0 A1 A2 A3 F S1S0F 00A0 01A1 10A2 11A3 A0 A2 A0 A2 S0=0 S1=0

18. 18 4-to-1 Mux using Transmission Gates A0 A1 A2 A3 S0=1 S1 F S1S0F 00A0 01A1 10A2 11A3 A0 A2

19. 19 4-to-1 Mux using Transmission Gates A0 A1 A2 A3 F S1S0F 00A0 01A1 10A2 11A3 A0 A2 A1 A3 S0=1 S1=1

20. 20 4-to-1 Mux using Transmission Gates with Enable (F=0 when En=0) A0 A1 A2 A3 A0 A2 S0=1 S1=1 EnS1S0F 0XX0 100A0 101A1 110A2 111A3 F En

21. 21 4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0) A0 A1 EnS1S0F 0XXZ 100A0 101A1 110A2 111A3 En=0X=0 Y=1 (To disable both TG) X Y X=En· S0 En=1X=S0 Y=S0 Y=En + En·S0 = En + S0

22. 22 4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0) A0 A1 EnS1S0F 0XXZ 100A0 101A1 110A2 111A3 X Y X=En· S0 En S0 Y=En + En·S0 = En + S0X Y

23. 23 4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0) A0 A1 EnS1S0F 0XXZ 100A0 101A1 110A2 111A3 X=En· S0 En S0 A2 A3 Y=En + En·S0 = En + S0

24. 24 4-to-1 Mux using Transmission Gates with Enable (F=Z when En=0) A0 A1 En S0 A2 A3 FEnS1S0F 0XXZ 100A0 101A1 110A2 111A3 S1

25. 25 Simplified 4-to-1 Mux using TGs with Enable (F=Z when En=0) S1 FEnS1S0F 0XXZ 100A0 101A1 110A2 111A3 A0 A1 A2 A3 A0 A2 S0 En Only Disable the 2 nd level X=En· S0X Y Y=En + En·S0 = En + S0

26. 26 Quadruple 2-to-1 Line Mux F[3:0] SEL En 2-to-1Mux (4-bit bus) A 3..0 B 3..0 A[3:0] B[3:0] EnSELF[3:0] 0X0000 10A[3:0] 11B[3:0]

27. 27 Quadruple 2-to-1 Line Mux EnSELF[3:0] 0X0000 10A[3:0] 11B[3:0] SEL B0B0 A0A0 F0F0 B3B3 A3A3 F3F3 B1B1 A1A1 F1F1 B2B2 A2A2 F2F2 En F x =A x ·En·SEL+B x ·En·SEL

28. 28 Design Canonical Form w/ MUX F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 8-to-1Mux S2S2 A4A4 A5A5 A6A6 A7A7 0 0 0 0 1 1 1 1 Each input in a MUX is a minterm ABC

29. 29 Design Canonical Form w/ MUX ABF 00 01 10 11

30. 30 Design Canonical Form w/ MUX ABF 00C 01C 100 111 F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 En 4-to-1Mux A B CC0 1 Vdd

31. 31 Design Canonical Form w/ MUX BCF 00 01 10 11

32. 32 Design Canonical Form w/ MUX BCF 000 01A 101 11A F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 En 4-to-1Mux B CAA Vdd

33. 33 Demultiplexers (DeMux) F A0A0 A1A1 A2A2 A3A3 S1S1 S0S0 4-to-1Mux A D0D0 D1D1 D2D2 D3D3 S1S1 S0S0 1-to-4DeMux

34. 34 DeMux Operations S1S0D3D2D1D0 00000A 0100A0 100A00 11A000 A D0D0 D1D1 D2D2 D3D3 S1S1 S0S0 1-to-4DeMux

35. 35 DeMux Operations S1S0D3D2D1D0 00000A 0100A0 100A00 11A000 D1 D2 D3 A S1 S0

36. 36 DeMux Operations w/ Enable EnS1S0D3D2D1D0 0XX0000 100000A 10100A0 1100A00 111A000 D1 D2 D3 A S1 S0 En