1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Multiplexers CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff HW 6 is out It is due on Monday (Oct 14) Wednesday (Oct 16)

4. Administrative Stuff HW 7 is out It is due next Monday (Oct 21)

5. Administrative Stuff Midterm Exam #2 When: Monday October 28. Where: This classroom What: Chapters 1, 2, 3, 4 and 5.1-5.4 The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).

6. 2-1 Multiplexer (Definition) Has two inputs: x 1 and x 2 Also has another input line s If s=0, then the output is equal to x 1 If s=1, then the output is equal to x 2

7. Graphical Symbol for a 2-1 Multiplexer f s x 1 x 2 0 1 [ Figure 2.33c from the textbook ]

8. Truth Table for a 2-1 Multiplexer [ Figure 2.33a from the textbook ]

9. Let’s Derive the SOP form

11. s x 1 x 2 Where should we put the negation signs?

12. Let’s Derive the SOP form s x 1 x 2

13. Let’s Derive the SOP form s x 1 x 2 f (s, x 1, x 2 ) = s x 1 x 2 +++

14. Let’s simplify this expression f (s, x 1, x 2 ) = s x 1 x 2 +++

15. Let’s simplify this expression f (s, x 1, x 2 ) = s x 1 x 2 +++ f (s, x 1, x 2 ) = s x 1 (x 2 + x 2 )s (x 1 +x 1 )x 2 ++

16. Let’s simplify this expression f (s, x 1, x 2 ) = s x 1 x 2 +++ f (s, x 1, x 2 ) = s x 1 (x 2 + x 2 )s (x 1 +x 1 )x 2 ++ f (s, x 1, x 2 ) = s x 1 s x 2 +

17. Circuit for 2-1 Multiplexer f x 1 x 2 s f s x 1 x 2 0 1 (c) Graphical symbol (b) Circuit [ Figure 2.33b-c from the textbook ] f (s, x 1, x 2 ) = s x 1 s x 2 +

18. More Compact Truth-Table Representation 0000 0010 0101 0111 1000 1011 1100 1111 (a)Truthtable sx1x1 x2x2 f (s, x 1, x 2 ) [ Figure 2.33 from the textbook ] 0 1 f (s, x 1, x 2 ) s x1x1 x2x2

19. 4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3

20. Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

21. The long-form truth table

22. [http://www.absoluteastronomy.com/topics/Multiplexer]

23. 4-1 Multiplexer (SOP circuit) [ Figure 4.2c from the textbook ] f = s 1 s 0 w 0 + s 1 s 0 w 1 + s 1 s 0 w 2 + s 1 s 0 w 3

24. 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer [ Figure 4.3 from the textbook ]

25. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

26. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

27. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

28. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer f s1s1 s0s0 w0w0 w1w1 w2w2 w3w3

29. That is different from the SOP form of the 4-1 multiplexer shown below, which uses less gates

30. w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f 16-1 Multiplexer [ Figure 4.4 from the textbook ]

31. Synthesis of Logic Circuits Using Multiplexers

32. 2 x 2 Crossbar switch x 1 x 2 y 1 y 2 s [ Figure 4.5a from the textbook ]

33. 2 x 2 Crossbar switch x 1 x 2 y 1 y 2 s=0 x 1 x 2 y 1 y 2 s=1

34. x 1 0 1 x 2 0 1 s y 1 y 2 [ Figure 4.5b from the textbook ] Implementation of a 2 x 2 crossbar switch with multiplexers

36. x1x1 x2x2 s y1y1 y2y2

37. Implementation of a logic function with a 4x1 multiplexer [ Figure 4.6a from the textbook ] f w 1 0 1 0 1 w 2 1 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 0

38. Implementation of the same logic function with a 2x1 multiplexer [ Figure 4.6b-c from the textbook ] (b) Modified truth table 0 1 0 0 1 1 1 0 1 fw 1 0 w 2 1 0 f w 2 w 1 0 1 f w 1 w 2 w 2 (c) Circuit

39. The XOR Logic Gate [ Figure 2.11 from the textbook ]

40. The XOR Logic Gate

41. Implemented with a multiplexer f

42. The XOR Logic Gate Implemented with a multiplexer x y f

43. The XOR Logic Gate Implemented with a multiplexer x y f These two circuits are equivalent (the wires of the bottom and gate are flipped)

44. In other words, all four of these are equivalent! x y f x y f x y f f w 1 0 1 w 2 1 0

45. [ Figure 4.7a from the textbook ] 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 Implementation of another logic function

46. [ Figure 4.7a from the textbook ] w 3 w 3 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 Implementation of another logic function

47. [ Figure 4.7 from the textbook ] w 3 w 3 f w 1 0 w 2 1 (a) Modified truth table (b) Circuit 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3

48. Another Example (3-input XOR)

49. [ Figure 4.8a from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1

50. [ Figure 4.8a from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 2 w 3  w 2 w 3 

51. [ Figure 4.8 from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers (a) Truth table 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 2 w 3  w 2 w 3  f w 3 w 1 (b) Circuit w 2

52. 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

53. 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

54. f w 1 w 2 (a) Truth table (b) Circuit 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9 from the textbook ]

55. Multiplexor Synthesis Using Shannon’s Expansion

56. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 Three-input majority function [ Figure 4.10a from the textbook ]

57. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 0 1 f w 1 Three-input majority function [ Figure 4.10a from the textbook ]

58. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 0 1 f w 1 w 2 w 3 w 2 w 3 + Three-input majority function [ Figure 4.10a from the textbook ]

59. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 (b) Circuit 0 1 f w 1 w 2 w 3 w 2 w 3 + f w 3 w 1 w 2 (b) Truth table Three-input majority function [ Figure 4.10 from the textbook ]

60. Three-input majority function f w 3 w 1 w 2

61. Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:

62. Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:

63. Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form: cofactor

64. Shannon’s Expansion Theorem (Example)

65. Shannon’s Expansion Theorem (Example) (w 1 + w 1 )

66. Shannon’s Expansion Theorem (Example) (w 1 + w 1 )

67. Shannon’s Expansion Theorem (In terms of more than one variable) This form is suitable for implementation with a 4x1 multiplexer.

68. Another Example

69. Factor and implement the following function with a 2x1 multiplexer

71. w f [ Figure 4.11a from the textbook ]

72. Factor and implement the following function with a 4x1 multiplexer

74. [ Figure 4.11b from the textbook ]

75. Yet Another Example

76. Factor and implement the following function using only 2x1 multiplexers

79. f g h w1w1

82. g 0 w3w3 w2w2 h w3w3 1 w2w2

83. Finally, we are ready to draw the circuit g 0 w3w3 w2w2 h w3w3 1 w2w2 f g h w1w1

84. g 0 w3w3 w2w2 h 1 f w1w1

85. w 2 0 w 3 1 f w 1 [ Figure 4.12 from the textbook ]

86. Questions?

87. THE END