1. Encoder, Tristate Driver

2. Outline Review: demo decoder FPGA example Encoder Priority Decoder
Demo Encoder, problems
Encoder using for loop
Priority Decoder
Application of Priority Decoder
Tristate Buffer
Implementation of a MUX using Tri-state buffer

3. Definition of an Encoder
2n input lines
n output lines
Performs the inverse operation of a decoder

4. Example of an Encoder

5. Implementation of an Encoder
Focus on one output at a time
x=D4+D5+D6+D7

6. Implementation of an Encoder
Focus on one output at a time
y=D2+D3+D6+D7

7. Implementation of an Encoder
Focus on one output at a time
z=D1+D3+D5+D7

8. Uncertainty of an Encoder
What if all the input lines are 0?
Use a valid bit
What if more than one input line are high?
Use priority—certain bits are more important than other bits

9. encode83a.v
Check is present.

10. encode83a_top.v
Turn off the decimal bit if the input is not valid

11. Demonstrate encode83a.v Input: 00000000 (decimal bit is off)
Intput: (Get 001)
Intput: (Still get 001)

12. Priority Encoder
Not a Valid State

13. Karnaugh Map

14. Karnaugh Map

15. Circuit Implementation

16. Write a for loop to
Implement encoder.
typo, should be a[i] as opposed
to x[i].
y will be set to I if ith bit of a is a 1.

17. Corrected Verilog

18. Application of Priority Encoder: 3 bit ADC

19. Three State Gate Possible state: 1, 0, high impedance state!
The output appears disconnected from the input

20. Application of Tri-State Gate
You can not make a connection like this
Unless you use a tri-state device!