Design guidelines for EMC of Components

Design guidelines for EMC of Components

Summary Which problems? EMC Guidelines at PCB level
IC Guidelines for low emission IC Guidelines for low immunity Starcore case study April 17

EMC management EMC should be taken into account at early design stage…
K. Armstrong, Advanced PCB design and layout for EMC April 17

EMC guidelines Power integrity (PI) Signal integrity (SI)
Which problems? Know your enemy Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS Conducted emission (CE) Integrated circuits / electronic applications Radiated immunity (RI) Radiated emission (RE) Remark: even these problems are different, they can have the same root cause. Soving one of these problem can help to solve other problems. Example: SI, PI, CE, REproblems can be related to a bad PCB design of power or ground plane design, return path of the current not ensured  SI and PI problems. As common mode current appears, an important radiated emission can be produced. Oter example where SI, PI, RE, CE and CI, RI can be related. The design of the power and ground plane of the application is not good and an antiresonance appears. The IC can excite these antiresonance and generate an important voltage flcutuation of Vdd  PI, SI and CE problem. As the power plane voltage fluctuates, the cavity forms by the power and ground plane can act as a parasitic antenna  RE problem. If a cnducted disturbance is applied on the power plane at the PCB antiresonance frequency, a large voltage fluctuation appear and disturb the circuit operation  CI problem. At this frequency, the power and ground plane acts as parasitic but efficient antenna, able to couple a radiated disturbance  RI problem. Conducted immunity (CI) April 17

EMC guidelines at PCB level
Signal integrity (SI) issue Example: voltage measurement at 3 terminals of two 20 cm long parallel PCB tracks. The first line is excited by a pulse generator, the second is terminated by two resistive loads. Origin of effects on both lines ?

Signal integrity (SI) issue Let’s consider a transmission along two conductors = 2-conductor transmission line. Let’s suppose an homogeneous lossless line Equivalent model: z L ZG I(z,t) Interconnect VG ZL I(z,t) Thevenin generator Transmission line Load The voltage and current on each point of the line is superposition of a forward and backward voltage, travelling in opposite directions.

At generator side (input): At generator side (input):
EMC guidelines at PCB level Signal integrity (SI) issue The voltage at each point of the line depends on the reflection coefficient at each line terminals: Transient behavior of voltage at each line terminals: At generator side (input): At generator side (input): Complex transient behavior related to the reflection coefficient on each extremities and transmission line discontinuities April 17

Overshoot / Undershoot Overshoot / Undershoot
EMC guidelines at PCB level Signal integrity (SI) issue Analysis of the round-trip period of the wave along the line Time (ns) Source Load VL(0)=0V L/v 2L/v Vload t L/v 3L/v Overshoot / Undershoot Vsource t 2L/v 4L/v Overshoot / Undershoot 8 April 17

Signal integrity (SI) issue Zc ; Tp VG VL Criterion for SI issue: if Tr is the rising or falling time of a signal, SI issues due to the propagation of the EM wave along the transmission line arise if: Overshoot VL or VG Vdd VIH Undershoot Undetermined level VIL Ringing t Longer setting time April 17

Signal integrity (SI) issue K. Armstrong, Advanced PCB design and layout for EMC April 17

Ensuring Signal integrity – Rule 1 Cancel reflection coefficient at each line terminals by impedance matching Impedance matching of a uniform transmission line with constant characteristic impedance Zc. Practical designs for a digital transmission: Zc Rpd Ct Vcc Rs : serial resistor= Rdriver - Zc Zc Rs Rpd Rpd : pull down resistor = Zc April 17

Is it better to use wide or narrow trace ?
EMC guidelines at PCB level Ensuring Signal integrity – Rule 2 Control the characteristic impedance of (2-conductor) transmission line (PCB track, package)  avoid line discontinuities Microstrip line configuration: W I εr t h Ideal ground plane Is it better to use wide or narrow trace ? April 17

Ensure a controlled and short return current path.
EMC guidelines at PCB level Ensuring Signal integrity – Rule 3 Ensure a controlled and short return current path. Place a full ground plane in microstrip line. Avoid slot in return plane (e.g. ground plane) Keep a symmetry (avoid unbalance in the return current path) CORRECT BAD April 17

SI design rule violation
EMC guidelines at PCB level Ensuring Signal integrity – Rule 3 Example: a microstrip line routed over 2 separated power planes. SI design rule violation From ECST Broadcheck – April 17

Signal integrity (SI) - Crosstalk Let’s consider 2 traces separated by a distance d. Trace 1 (emitter) d Trace 2 (victim) W W I1’ I1 Crosstalk (near-field coupling) I2 εr V h Parasitic return current path “Normal” return current path Emitter trace Victim trace VE RS RL RNE RFE Near end Far end VNE VFE CM LM Capacitive coupling Inductive coupling Equivalent model: 15 April 17

Validity of quasi-static approximation
EMC guidelines at PCB level Signal integrity (SI) - Crosstalk Low frequency model (quasi-static approximation  propagation effects neglected) VNE VFE Validity of quasi-static approximation 16 April 17

Increase the isolation between emitter and victim lines
EMC guidelines at PCB level Ensuring Signal integrity – Rule 4 Increase the isolation between emitter and victim lines Increase the distance between traces (rule 3 W = “the separation between traces must be 3 times the width of the trace as measured from centerline to centerline of two adjacent traces”) < 3W W W t h (εr = 4.5) Substrate ground 17 April 17

Power integrity (PI) issue – Power Distribution Network Bulk capacitor (Low frequency) HF capacitor (ceramic) PCB – Power / ground plane Package and IC Power source Voltage converter / regulator Ferrite Vdd Vss Ground reference 1 µF – 10 mF 100 nF – 1 nF 1 nF Transistors, gates, interconnects 18 April 17

Power integrity (PI) issue Power supply source (regulator, DC-DC converter) ΔVdd PDN Vss Vdd i(t) Circuit PDN Noisy Integrated circuit Power supply bounce Delta-I noise ΔVss 19 April 17

Power integrity (PI) issue Example: on-chip measurement of the power supply voltage fluctuation of a digital circuit High frequency contribution Low frequency contribution Switching Switching Switching Noise with a large frequency content and some major resonance modes 20 April 17

Power supply voltage bounce: Target frequency range
EMC guidelines at PCB level Power integrity (PI) issue Equivalent model of a PDN (the most basic model…) PDN Circuit Vdd Power supply voltage bounce: ZPDN ΔVdd IIC gnd Ensuring power integrity relies on the control of a low impedance of the PDN. A target impedance ZT can be defined as a design objective: ZPDN Zt Frequency Target frequency range 21 April 17

Ensuring Power integrity – Rule 1 Reduce interconnect parasitic (mainly inductance) of power and ground connections Use traces as wide as possible for Vdd and Vss connections i.e. use power and ground planes Be careful of the common impedance of Vdd and Vss connections (finite impedance, even for ground plane): Single point grounding with serial circuits Direct grounding to a reference ground plane 22 April 17

Ensuring Power integrity – Rule 2 Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand) Principle: Voltage bounce v(t) Local charge tank Voltage regulator Decoupling capacitor IC Vdd Vss Vdd Vss PCB i(t) In time domain Large capacitors react rapidly to charge demand. In frequency domain Large capacitors reduce PDN impedance. 23 April 17

Ensuring Power integrity – Rule 2 Effect of on-board capacitors: X7R 50 V ceramic capacitors No decoupling Customer’s specification Parasitic emission (dBµV) 80 10 – 15 dB 70 60 nF decoupling 50 Efficient on one decade 100 µF electrolytic capacitor 40 30 20 10 -10 1 10 100 1000 Frequency (MHz) 24 April 17

Ensuring Power integrity – How choosing decoupling capacitor If ideal capacitor, only one decoupling capacitor would be enough: Cdec: the minimum capacitor able to provide a current to the circuit without any large voltage fluctuations. ΔVddmax : max allowed voltage fluctuation ΔI : current peak absorbed by the circuit tr : rise time of the current peak However, due to the parasitic elements associated to decoupling capacitors, its efficiency frequency range is limited or it can not respond to rapid current demand. It is necessary to place several decoupling capacitors in parallel to increase the efficiency frequency range of the decoupling. 25 April 17

Ensuring Power integrity – How choosing decoupling capacitor Methodology to optimize the choice of decoupling capacitors: Board model Regulator model Circuit(s) model Define Zt PDN without decoupling model Define freq. range of decoupling Fmin  Fmax Compute ZPDN YES If ZPDN(f) > Zt for f in [Fmin;Fmax] NO Add capacitor(s) and/or change capa values Capacitors model Power integrity OK – Decoupling budget April 17

Board + IC without decap
EMC guidelines at PCB level Ensuring Power integrity – How choosing decoupling capacitor Example: decoupling of a 16 bit microcontroller (dspic33F). The circuit produces a significant amount of noise over the range 1 – 500 MHz. We select Zt = 2 Ω. IC Current (1 Ω probe) Z PDN (VNA measurement) Board + IC without decap ZT The max current is 76 dBµA  6.3 mA. If Zpdn = 2 ohms, the voltage fluctuation = 12.6 mV. With 6×100 nF decap 27 April 17

Ensuring Power integrity – Anti-resonance issue What happens if 2 “real” capacitors are placed in parallel ? Fantires The impedance around the antiresonance frequency can be computed as follows: C1 is very small compared to L1 (L1 and C1 have already resonated, at 22 MHz). The equivalent circuit, if the resistances R1 and R2 are neglected, becomes L2 and C2 in serie, with L2 in parallel. The equivalent impedance is : Z (f=Fantires) = j*L1*w*(1-L2C2*W²)/(1-(L1+L2)*C2*w²), w = 2*pi*freq. When w² = 1/((L1+L2)*C2), Z becomes infinite, this is the antiresonance. Fantires = 2*pi/sqrt((L1+L2)*C2) = 50 MHz The impedance does not become infinite due to the capacitor ESR, but the impedance reaches a local maximum, which could be larger than the target impedance. If a current (delivered by the circuit itself or an external disturbance source) excites this circuit at the antiresonance frequency, a large voltage fluctuation can be produced. Fantires = 28 April 17

What is the cause of this anti-resonance ?
EMC guidelines at PCB level Ensuring Power integrity – Anti-resonance issue Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. The PDN impedance measurement shows an anti-resonance at 162 MHz PDN equivalent model Fantires The model is formed by: the board model (the cavity formed by Vdd and Vss planes), the 6 * 100 nF decoupling capacitors (we model them by an equivalent capacitors) and the circuit model (on-chip capacitor and package inductance). The element values have been determined from VNA measurements. If we analyze the circuit, the anti-resonance is produced by the on-chip capacitor (Cchip) and several inductive contribution: package inductance (Lpackage), board and decoupling capacitor inductances (Lboard // LCdec). Actually, as Loboard >> LCdec, the board inductance has only a small contribution. According to this model, the anti-resonance frequency should be equal to: Fantires = 2*pi/sqrt((Lpackage+LCdec)*Cchip) = 168 MHz. This anti-resonance is linked to several elements of the PDN. The circuit has an important contribution on the appearance of this anti-resonance. What is the cause of this anti-resonance ? April 17

Ensuring Power integrity – Anti-resonance issue Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. Measurement of power supply voltage in time domain (16 I/O pads switch simultaneously). The oscilloscope capture shows the output signal of a I/O pad (C2), which switches at 5.7 MHz, and the power supply voltage measured on Vdd power plane (C1). At each I/O switching, a voltage bounce appears. IT looks like a oscillatory signal with a constant pseudo-period which is damped after several period. If we analyze in detail this pseudo-oscillation, we could verify that its frequency is about 162 MHz, the anti-resonance frequency of the PDN. The circuit activity produces a current that circulated across the PDN. The circuit current has large spectrum (see slide 25, from 1 to 500 MHz). The spectral content between 1 and 100 MHz is correctly filtered by the small PDN impedance. However, the noise produced around 160 MHz is not filtered by the PDN because of the antiresonance. The circuit is able to activate this resonance mode, so that’s why we see clearly an oscillation with such a frequency. Even if the PDN impedance tends to increase, the contribution of higher harmonics is not visible because the current amplitude tends to rapidly falls down. The different elements of the PDN introduced some losses, so that’s why the oscillatory is damped quite rapidly. April 17

Ensuring Immunity – Anti-resonance issue Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. Measurement of conducted immunity (harmonic signal coupled on power supply plane according to DPI standard). At each harmonic frequency, the disturbance power is increased until a circuit failure arises. Max. Power This antiresonance alters also the immunity of the circuit to conducted interferences. Here an harmonic conducted interference is coupled to the Vdd plane of the dspic test board. At several frequency, the amplitude of the disturbance is increased until a failure arises. The circuit presents a failure at a lower level around 160 MHz. This weakness is not intrinsic to the circuit, but linked to the anti-resonance of the PDN. At this frequency, for a given disturbance amplitude, a larger voltage fluctuation is coupled on Vdd plane.

Radiated emission – basic mechanisms Radiated emissions come from interconnects excited by a transient current or voltage. They become parasitic antennas. Two basic radiated mechanisms: Dipole antenna (electric) high impedance load (I/O loaded by high impedance) E field proportional to length l Loop antenna (magnetic) Low impedance load (power supply, I/O loaded by low impedance H field proportional to surface S Electric field Magnetic field Circuit I Circuit Clock VSS VDD Length l High Z load Surface S 32 April 17

Decomposition in 2 distinct propagation modes
EMC guidelines at PCB level Radiated emission – basic mechanisms Differential vs. common radiated mode. Common mode appears when the return current path is not perfectly defined. If I1 ≠ I2 1 2 Id Differential mode I1 Interco 1 I2 Decomposition in 2 distinct propagation modes 1 2 Ic Interco 2 Common mode 33 April 17

Main conclusions about radiation mechanisms ?
EMC guidelines at PCB level Radiated emission – basic mechanisms Comparison of common and differential radiated mode. Let’s consider electrically 2 short parallel interconnects (length L << λ): L=10 cm, d=2 mm, r = 1 m, ID = 50 mA, IC = 5 mA L: interconnect length d: interconnect separation f: frequency of excitation current r: distance between E field measurement point and interconnect centers ID and IC: differential and common mode currents ED and EC: differential and common mode radiation (E field) If all the current in interconnect 1 does not return along interconnect 2 (a parasitic coupling exists with another interconnect), the dissymmetry induces a common mode current. Even if this common mode current is small (in this example Ic = 10% of ID, The common mode radiation remains larger than differential current over a large frequency range. Let’s suppose that the excitation current is produced by the dspic, a significant current exists between 1 MHz and 500 MHz. In that case, the common mode current is the main source of problem. It is essential to reduce coomon mode cuurent. It is more difficult to reduce radiated common mode than radiated differential mode, because the differential mode is identified easily (loop formed by an interconnect and the normal return path). To reduce differential mode, you only need to reduce the surface of the loop formed by these two interconnects. For common mode, the return paths are not obvious and linked to parasitic couplings. Many investigations must be done to identify the mechanisms of creation of common mode current. Moreover, as the return path is not designed, its length can be very long  often an efficient parasitic antenna. Both radiation mechanisms have a frequency dependent behavior (the proposed model is only valid if we consider electrically short interconnect, i.e. quasi static approximation). Otherwise, we should take into account the propagation of the wave along the transmission line formed by both interconnects. This frequency behavior makes the radiated emission a “high frequency” problem. Main conclusions about radiation mechanisms ? 34 April 17

Reducing radiated emission – Rule 1 Reduce parasitic antenna (length or surface) to reduce differntial and common mode radiation Identify current loops on PCB and reduce their surface. Place decoupling capacitors as close as possible to IC pins. Use power or ground plane to reduce current loop surface. Reduce the length of interconnects which carry high frequency signals. Circuit Circuit VDD VDD Decoupling capacitor VSS VSS Decoupling capacitor Id Id Large loop  High radiated differential mode Smaller loop  Reduced radiated differential mode 35 April 17

Control the current return path to reduce common mode
EMC guidelines at PCB level Reducing radiated emission – Rule 2 Control the current return path to reduce common mode Example 2: one differential output buffer with a non symmetrical routing Example 1: one Vdd pin but two Vss pins IVdd = IVSS1+IVSS2 Power Differential buffer I+ ≠ I- Circuit IVdd I+ VDD VSS2 D+ VSS1 D- I- IVss1 Parasitic coupling GND IVSS2 Ic 36 April 17

Use a “good” ground plane(s) to shield noisy interconnects
EMC guidelines at PCB level Reducing radiated emission – Rule 3 Use a “good” ground plane(s) to shield noisy interconnects Use coplanar or stripline configuration to shield noisy interconnect. A “good” reference plane is equipotential at any point ! Connect two reference plane witth same potential by vias regular interval less than λ/20 ! Correct connection between two planes with same potential Stripline configuration Ref plane line GND via Ref plane GND 37 April 17

Radiated emission – Case study Basic digital applications routed on a 2 layer board with the auto-router function of the board design tool. Only one 100 nF decoupling capacitor for all the application. Measurement of radiated emission in TEM cell. Limit CISPR25

Radiated emission – Case study Numerous EMC design rules violation: large power-ground loops, long fast clock interconnect, return path not ensured by a ground plane… Change the placement & routing of the board by starting to place Vdd/Vss and fast clock, add a ground plane on both side. Design rule violation examples: Large loop CMOS inverter Vdd connection Vss connection Equivalent surface of fast clock interconnect “High speed” clock source 39

Radiated emission – Case study Top layer Effect of placement & Routing improvement (still one 100 nF decoupling capacitor) -30 dB Bottom layer 40 April 17

+ or – effect depending on freq.
EMC guidelines at PCB level Radiated emission – Case study Effect of decoupling capacitors (one capacitor per circuit) Effect of GND vias density + or – effect depending on freq. ≈ -5 dB 41 April 17

Summary EMC can be improved at PCB level, mainly by an adequate placement and routing of rapid signals, power and ground references. Several EMC issues have the same root causes  one EMC design rule can solve several problems. The modeling is important to understand the problem and optimize solution. An accurate IC model is mandatory to manage EMC at PCB level. 42 April 17

Golden Rules for Low Emission
Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance Inductance is a major source of resonance Each conductor acts as an inductance Ground plane modifies inductance value (worst case is far from ground) Reducing inductance decreases SSN !! Lead: L=0.6nH/mm We detail four rules to reduce parasitic emission. The first one consists in decreasing the serial inductance. Inductance is a major component that creates resonance, and resonance is the source of conducted and radiated emission. The inductance is an intrinsic component of each conductor. When the conductor is far from ground, the inductance is increased. A bonding wire has approximately a 1nH/mm inductance. A supply line within the chip has a 0.2nH/mm inductance. Bonding: L=1nH/mm April 17

Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10nH Die of the IC bonding Long leads Far from ground PCB Flip chip package: L up to 3nH Short leads Die of the IC balls Add values for L package Close from ground Requirements for high speed microprocessors : L < 50 pH ! April 17

Rule 1: Power supply routing strategy B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs Correct Fail 9 I/O ports It reduces serial inductance  SSN. It reduces also inductive crosstalk between signal traces since supply pairs conducts returning signal current. A good ration for number of supply pairs on number of IO is about 8. April 17

Rule 1: Power supply routing strategy C) Place supply pairs close to noisy blocks Layout view Current density simulation Memory PLL Digital core VDD / VSS The good solution consists in the placement of VDD/VSS pad pairs. VDD/VSS rails should also be routed as close as possible. This increases decoupling capacitance. Also, multiple pairs significantly reduce the internal loops. April 17

Reduced contributions
Golden Rules for Low Emission Rule 1: Power supply routing strategy D) Place VSS and VDD pins as close as possible Current loop EM field to increase decoupling capacitance that reduces fluctuations to reduce current loops that provoke magnetic field Added contributions Reduced contributions Die Lead current EM wave currents The second important rule consists is placing VDD and VSS supply as close as possible from each others. This reduces the surface of the current loop which provokes immediate parasitic emission, in radiated mode. A very bad pin assignment consists in one VDD supply on one side, one VSS supply on the other side. This lead to a maximum emitted parasitic energy. Consequently, the current wires placed together almost cancel the magnetic field and significantly reduce the radiated signature of the IC. Gains higher than 20dB have been observed in TEM cell measurements. April 17

Case 1 : Infineon Tricore
Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: Case 1 : Infineon Tricore Case 2 : virtex II Add ration IO/supply IO (virtex II bcp de supply IO) Worst case not enough supply pairs, bad distribution & dissymmetry Not ideal Not enough supply for IOs : (core emission is lower than IO one) April 17

Rule 1: Power supply routing strategy Case study 2: 2 FPGA , same power supply, same IO drive, same characteristics Supply strategy very different ! More Supply pairs for IOs Better distribution courtesy of Dr. Howard Johnson, "BGA Crosstalk", April 17

Case 2: higher emission level (5 times higher)
Golden Rules for Low Emission Rule 1: Power supply routing strategy Case 1: low emission due to a large number of supply pairs well distributed Case 2: higher emission level (5 times higher) courtesy of Dr. Howard Johnson, "BGA Crosstalk", April 17

Rule 1: Power supply routing strategy 324-BGA (49 Vdd/Vss pairs) 208-BGA (31 Vdd/Vss pairs) Case study 3: conducted (150 ohms probe placed on Vdd) and radiated (TEM cell) emission from a microcontroller mounted in either & 208-BGA or a 324-BGA. Larger conducted emission from 208-BGA (less power supply pins) Larger radiated emission from 324-BGA (larger interconnects) E. Rogard and al., "Characterization and Modelling of Parasitic Emission of a 32-bit Automotive Microcontroller Mounted on 2 Types of BGA", IEEE EMC Symposium Austin, Texas, USA 2009 April 17

Rule 2: Add decoupling capacitance On chip decoupling capacitance versus technology and complexity: Intrinsic on-chip supply capacitance 100nF 65nm 90nm 10nF 0.18µm 0.35µm 1.0nF 100pF Devices on chip 10pF 100K 1M 10M 100M 1G Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF April 17

On-chip voltage measurement 1 ohm conducted measurement
Golden Rules for Low Emission Rule 2: Add decoupling capacitance Effect of on chip capacitance: smooth on-chip voltage fluctuation and reduce conducted emission. Example: two versions of a CMOS 90 nm digital core, Vdd = 1.2 V, same mounting board: Core 1: No on-chip decoupling capacitance Core 2 : Add 100 pF MIM decoupling capacitance On-chip voltage measurement 1 ohm conducted measurement 59 mV 27 mV A. Boyer (LAAS-CNRS) April 17

Rule 3: Reduce I/O noise Reduction of the fast rate of I/O current. Minimize the number of simultaneous switching lines (bus coding) Reduce di/dt of I/O by controlling slew rate and drive Tr1 Tr2 SR & Drive control Emission level f 1/Tr2 1/Tr1 April 17

Full Drive – High slew rate Reduced Drive – High slew rate
Golden Rules for Low Emission Rule 3: Reduce I/O noise Example: I/O buffer with Drive and slew rate control options: Full or reduced drive, high and limited slew rate. Impact of I/O options on timing waveform: Rise time = 2 ns Rise time = 8.6 ns Full Drive – High slew rate Reduced Drive – High slew rate April 17

What is the more « emissive » option ? The less emissive ?
Golden Rules for Low Emission Rule 3: Reduce I/O noise Impact of I/O options on timing waveform and output drive current: What is the more « emissive » option ? The less emissive ? April 17

Rule 3: Reduce I/O noise Comparison of conducted emission (1 ohm method)

Rule 3: Reduce I/O noise Comparison of conducted emission (1 ohm method) April 17

Origin of electromagnetic emission
Rule 4: Reduce SSN The switching of output buffer contributes to a large part of conducted and radiated emission. When several I/O switches simultaneously, their contributions tend to add: Simultaneous Switching Noise. Minimize the number of simultaneous switching lines (bus coding) Effect of the number of simultaneous switching buffers 16 output buffers, two different switching sequences. April 17

Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation Reduction or spreading of clock harmonics by frequency modulation. Example : sinus clock at Fc = 100 MHz vs modulated sinus clock: Reduction of narrow band RF energy Carrier frequency Fc = 100 MHz Modulation frequency FM = 1 MHz Frequency excursion dF = +/- 5 MHz  Modulation index md = 5 Spread spectrum over B Carson rule: 60 April 17

Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation In practice, a triangular signal is used as modulating signal. Freq. modulation ΔF Clock in Clock out Tc Tc+/-dt +/- dt Frequency Modulated clock Modulant t Carson rule applies also: TMod dP If Fmod < RBW (reso BW of the receiver): Modulated clock B Unmodulated clock 61

Predicted value of spreading reduction ?
Golden Rules for Low Emission Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation Real case study: FM-PLL block of the 32 bit microcontroller MPC 5604B from Freescale. PLL frequency set at 64 MHz. Measurement of near-field emission above the circuit. Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/ MHz. Receiver bandwidth = 1 KHz. 10 dB Predicted value of spreading reduction ? The RBW has no influence on the reduction since RBW is < Fmod. The receiver is enough narrowband to separate the different harmonic that composed the modulated signal. The power of the signal is spread over N harmonics centered around Fc = 64 MHz and separated by Fmod = 100 KHz. The FM-PLL is configured to have a peak-to-peak frequency excursion equal to 1.28 MHz. The modulation index is equal to According to Carson rule, the signal is spread over a freq range B equal to 1.28 MHz. With RBW = 1 KHz, according to the previous formula, we should obtain a power reduction of 10log(B/RBW) =31 dB ! But we don’t observe that , because the spread spectrum is not flat. Actually, with a triangular waveform, we can not obtain a pure flat spreading. The energry is spread on a finite number of harmonics. There are N = 1.28 MHz/0.1 MHz +1 = 27 harmonics over B. If we suppose that all the N harmonics spread over B have the same amplitude, their power is theoritically reduced by 11.4 dB. The measured reduction is equal to 10 dB. A. Boyer (LAAS-CNRS) 62 April 17

Average reduction of 64 MHz harmonics = 10.6 dB
Golden Rules for Low Emission Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation Real case study: Effect on emission spectrum Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/ MHz. Receiver bandwidth = 10 KHz. Average reduction of 64 MHz harmonics = 10.6 dB A. Boyer (LAAS-CNRS) 63 April 17

Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation The reduction amount is dependent of the receiver bandwidth RBW if the modulation frequency is less than RBW. Example: FM = 50 KHz, dF = +/ MHz. RBW = 1 KHz vs. RBW = 100 KHz. 3 dB With this FM parameters, the theoritical reduction of th emission is 17.4 dB, if the spread spectrum is supposed flat and if the RBW is less than Fmod (to separate each harmonics). As Fmod = 50 KHz, 2 successive harmonics are separated by 50 KHz. With RBW = 1 KHz, all the harmonics are separated. However, with RBW = 100 KHz, the receiver tends to superimpose 2 successive harmonics, so their power adds. Thus, the spreading reduction is degraded by 3 dB. A. Boyer (LAAS-CNRS) 64 April 17

Decoupling capacitance No rules to reduce susceptibility
Golden Rules for Low susceptibility Rule 1: Decoupling capacitance is also good for immunity Immunity level (dBm) DPI aggression of a digital core Reuse of low emission design rules for susceptibility Efficiency of on-chip decoupling combined with resistive supply path Decoupling capacitance Substrate isolation No rules to reduce susceptibility Work done at Eseo France (Ali ALAELDINE) Frequency April 17

Golden Rules for Low susceptibility
Rule 2: Isolate Noisy blocks Analog Standard cells Noisy blocks Far from noisy blocks Bulk isolation Separate supply Why ? To reduce the propagation of switching noise inside the chip To reduce the disturbance of sensitive blocks by noisy blocks (auto-susceptibility) How ? by separate voltage supply by substrate isolation by increasing separation between sensitive blocks By reducing crosstalk and parasitic coupling at package level The 4th important rule consists in trying to identify the noisy blocks, and try our best to isolate them. In terms of EMC, we concentrate on fast signals which switch high power. We try to supply these circuits by separate supplies, and if possible, isolate substrate noise conduction by a bulk isolation, a feature available starting 0.18µm. April 17

Rule 2: Isolate Noisy blocks separate supply substrate isolation increasing separation between sensitive blocks From Prof. Adrijan Barić , FER Zagreb EMC Compo 2011 April 17

Rule 3: Improve noise immunity of IOs Add Schmitt trigger on digital input buffer Use differential structures for analog and digital IO to reject common mode noise 2 dB Schmitt trigger April 17

Design guidelines for EMC of IC
Case study – Starcore floorplan improvement The Starcore is 16-bit micro-controller used in automotive industry: 16 bit MPU with 16 MHz external quartz, on-chip PLL providing internal 133 MHz operating clock 128 Kb RAM, 3 general purpose ports (A, B, C, 8 bits), 4 analog inputs 12 bits, CAN interface SIGNAL Description VDD Positive supply VSS Logic Ground VDD_OSC Oscillator supply VSS_OSC Oscillator ground PA[0..7] Data port A (programmable drive) PB[0..7] Data port B (programmable drive) PC[0..7] Data port C (programmable drive) external 66MHz data/address ADC In[0..3] 4 analog inputs (12 bit resolution) CAN Tx CAN interface (high power, 1MHz) CAN Rx XTL_1, XTL_2 Quartz oscillator 16MHz CAPA PLL external capacitance RESET Reset microcontroller April 17

Case study – Starcore floorplan improvement Several tests were conducted by the customer and a huge list of problems appeared. Now that you learnt some rules about low emission floor-planning, you are probably able to understand the origin of the listed problems. In this case study, you act as an EMC engineer which is called urgently to improve the floor-planning of the chip (without changing the chip layout which would cost too much), in order to save the contract. Warning: Reliability problems (over current) on pin 23 Ground bounce: voltage drop around 500mV (spec: 50mV) VDD bounce: voltage drop around 700mV (spec 50mV) ADC measured resolution: 6 bits (required 10 bits) CAN bus erratic problems Oscillator PLL sometimes do not lock

Case study – Starcore floorplan improvement SIGNAL Description Emission Susceptibility Remark Assign to VDD Positive supply + A l’opposé, 1 seule paire, sur les diagonales VSS Logic Ground VDD_OSC Oscillator supply Réassigner broches Osc près Bloc Osc. VSS_OSC Oscillator ground à éloigner du CAN PA[0..7] Data port A (programmable drive) PB[0..7] Data port B (programmable drive) PC[0..7] Data port C (programmable drive) external 66MHz data/address Mettre une paire Vdd/Vss à proximité ADC In[0..3] 4 analog inputs (12 bit resolution) +++ Paire alim dédiée VddA/VssA, repositionner près du bloc ADC CAN Tx CAN interface (high power, 1MHz) CAN Rx XTL_1, XTL_2 Quartz oscillator 16MHz CAPA PLL external capacitance RESET Reset microcontroller - Mettre dans un coin The first action is to identify which block is a noisy block, which part is a sensitive part.

Case study – Starcore floorplan improvement Then you can try to assign the various I/os to specific pins. Place your solution here. Several good solutions exist. Was this an imaginary scenario? No! Most of the contents of this course come from severe ignorance of EMC problems, that are found at the end of the design cycle and may induce losses of millions of Euro.

Design guidelines for EMC of Components

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Design guidelines for EMC of Components

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