1. ASIC Design Introduction - 1 The history of Integrated Circuit (IC) The base for such a significant progress –Well understanding of semiconductor physics –Capability of purifying the material –Fine control of IC manufacture process One of the most important inventions in our modern life –IC has changed our life Personal computer Cellular phone Internet Wireless communication Automobile electronics Medical applications

2. ASIC Design Introduction - 2 In 1947, John Bardeen, Walter Brattain, and William Shockley invented the first transistor.

3. ASIC Design Introduction - 3 In 1958, Jack Kilby and Robert Noyce invented the first integrated circuit.

4. ASIC Design Introduction - 4

5. ASIC Design Introduction - 5 Moore ’ s law The performance and density are doubled every 18 months. Moore ’ s law has held for the past 40 year. Let ’ s look at –Moore ’ s law in microprocessors –Moore ’ s law in chip capacity –Die size growth –Wafer size (12 inch)

6. ASIC Design Introduction - 6 Moore ’ s Law in Microprocessors 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 19701980199020002010 Year Transistors (MT) 2X growth in 1.96 years! Courtesy, Intel

7. ASIC Design Introduction - 7 Evolution in DRAM Chip Capacity 1.6-2.4  m 1.0-1.2  m 0.7-0.8  m 0.5-0.6  m 0.35-0.4  m 0.18-0.25  m 0.13  m 0.1  m 0.07  m human memory human DNA encyclopedia 2 hrs CD audio 30 sec HDTV book page 4X growth every 3 years!

8. ASIC Design Introduction - 8 Die Size Growth 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 19701980199020002010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years Courtesy, Intel

9. ASIC Design Introduction - 9 Production year 200220032004200520062007 MPU Gate length (nm) 756553454035 Clock (GHz) 2.33.14.05.25.66.7 Metal layers 888999 Supply voltage (V) 1.0 0.9 0.7 International Technology Roadmap for Semiconductors (ITRS)

10. ASIC Design Introduction - 10 Technology has moved into the deep submicron (DSM) feature size –The state of the art technology is 22nm feature size –Face many new IC design issues due to the increasing performance requirement and DSM feature size Design for manufacture (DFM) New device model Performance driven design Distributed circuit parameters Power dissipation More powerful CAD tools

11. ASIC Design Introduction - 11 Exploding Mask Costs Raster scan patterning exposure time for a 110mm x 110 mm mask is 6.5 hrs and 20 hrs with fine granularities (60nm vs. 120nm pixel size) Largest cost contribution to mask making is mask exposure time (capital cost ~$20M) RET is being absorbed by CAD vendors into layout verification / tape-out suites. RET may move up into routing, placement Source: Thomas Weisel Partners $800K-1.2M$1-2M$500K-1M$200-400KCost.9 µ m 2004.065 µ m.13 µ m.18 µ m Node 200720021999Year 256GB1024GB64GB16GBData

12. ASIC Design Introduction - 12 Power Dissipation P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 197119741978198519922000 Year Power (Watts) Courtesy, Intel Power delivery and dissipation will be prohibitive

13. ASIC Design Introduction - 13 Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel

14. ASIC Design Introduction - 14 Custom and semi-custom ICs –Custom designed microprocessors, such as Intel Pentium –Semi-custom designed ICs, such as gate array and FPGA Specific circuit structures are introduced to shorten design cycle Tread-off between the design quality and design time ASIC chip usually uses custom design to increase the performance and to reduce the chip cost Prototype development usually use the semi-custom design to reduce the design cycle

15. ASIC Design Introduction - 15 Intel Pentium (IV) Microprocessor (custom design)

16. ASIC Design Introduction - 16 Design flow –Traditional design flow The design tasks usually can be divided into separated stages Single direction, usually a top-down strategy –The interplay between different design tasks becomes important Physical phenomena and circuit facts should be considered at high design levels –Floorplanning is a challenge

17. This chart only presents the basic tasks in the design process. However, the flow of design tasks is not a single direction. The influence of the late design stage can affect the early ones.

18. Design perspectives

19. ASIC Design Introduction - 19 CAD tools –Most of today ’ s IC design are done by using CAD tools. The major CAD tools are: Cadence –good physical design –synthesis Synopsis –good high level synthesis –physical layout Mentor Graphics –analog IC –verification Magma –physical design, good in time closure