1. Non-linear application Inverting Schmitt Trigger
non-linear application:schmitt trigger
Non-linear application Inverting Schmitt Trigger
Schmitt Trigger - +
Positive Feedback
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2. Non-linear application Schmitt Trigger
(b) Input Voltage of Schmitt Trigger
Vo(V) 15
-15 t
VS(V)
7.5
-7.5
(a) Transfer Characteristic of Schmitt Trigger
Vo(V)
VS(V)
-7.5
7.5
-10 10 15
-15
(c) Output Voltage of Schmitt Trigger
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3. Zero Crossing Detector
Zero-crossing detector is an applied form of comparator. Either of the op-amp basic comparator circuits discussed can be employed as the zero-crossing detector provided the reference voltage Vref is made zero. 
Zero-crossing detector using inverting op-amp comparator is depicted in figure. The output voltage waveform shown in figure indicates when and in what direction an input signal vin crosses zero volt. In some applications the input signal may be low frequency one (i.e. input may be a slowly changing waveform).
In such a case output voltage vOUT may not switch quickly from one saturation state to the other. Because of the noise at the input terminals of the op-amp, there may be fluctuation in output voltage between two saturation states (+ Vsat and – Vsat voltages).
Thus zero crossings may be detected for noise voltages as well as input signal vin. Both of these problems can be overcome, if we use regenerative or positive feeding causing the output voltage vout to change faster and eliminating the false output transitions that may be caused due to noise at the input of the op-amp.

5. Analog-to-Digital Converter (ADC)
And
Digital-to-Analog Converter (DAC)

6. 1.    DAC
In an electronic circuit, a combination of high voltage (+5V) and low voltage (0V) is usually used to represent a binary number. For example, a binary number 1010 is represented by
Weighting 23 22 21 20
Binary Digit 1
State
+5V 0V
DACs are electronic circuits that convert digital, (usually binary) signals (for example, ) to analog electrical quantities (usually voltage) directly related to the digitally encoded input number.

7. DACs are used in many other applications, such as voice synthesizers, automatic test system, and process control actuator. In addition, they allow computers to communicate with the real (analog) world.

8. Register: Use to store the digital input (let it remain a constant value) during the conversion period.
Voltage: Similar to an ON/OFF switch. It is ‘closed’ when the input is ‘1’. It is ‘opened’ when the input is ‘0’.
Resistive Summing Network: Summation of the voltages according to different weighting.
Amplifier: Amplification of the analog according to a pre-determined output voltage range. For example, an operation amplifier

9. The two most popular types of resistive summing networks are:
·   Weighted binary resistance type, and
·   Ladder resistance (R-2R) type

10. BINARY WEIGHTED D TO A CONVERTER
A typical digital-to-analog converter outputs an analog signal, which is usually voltage or current, that is proportional to the value of the digital code provided to its inputs. Most DAC's have several digital input pins to receive all the bits of its input digital code in parallel (at the same time).  Some DAC's, however, are designed to receive the input digital data in serial form (one bit at a time), so these only have a single digital input pin. 
   
A simple DAC may be implemented using an op-amp circuit known as a summer, so named because its output voltage is the sum of its input voltages. Each of its inputs uses a resistor of different binary weight, such that if R0=R, then R1=R/2, R2=R/4, R3=R/8,.., RN-1=R/(2N-1).  The output of a summer circuit with N bits is:    

11. The R/2R DAC

12. Vo = VR/2N (SN-12N-1 + SN-22N-2+...+S020).
The input circuit is a remarkable design, known as an R-2R ladder network. It has several advantages over the basic summer circuit we saw first:
Only two resistance values are used anywhere in the entire circuit. This means that only two values of precision resistance are needed, in a resistance ratio of 2:1. This requirement is easy to meet, and not especially expensive. 
The input resistance seen by each digital input is the same as for every other input. The actual impedance seen by each digital source gate is 3R. With a CMOS gate resistance of 200 ohms, we can use the very standard values of 10k and 20k for our resistors. 
The circuit is indefinitely extensible for binary numbers. Thus, if we use binary inputs instead of BCD, we can simply double the length of the ladder network for an 8-bit number (0 to 255) or double it again for a 16-bit number (0 to 65535). We only need to add two resistors for each additional binary input. 
The circuit lends itself to a non-inverting circuit configuration. Therefore we need not be concerned about intermediate inverters along the way. However, an inverting version can easily be configured if that is appropriate. 
One detail about this circuit: Even if the input ladder is extended, the output will remain within the same output voltage limits. Additional input bits will simply allow the output to be subdivided into smaller increments for finer resolution. This is equivalent to adding inputs with ever-larger resistance values (doubling the resistance value for each bit), but still using the same two resistance values in the extended ladder.
Vo =   VR/2N (SN-12N-1 + SN-22N S020).

13. Vo = VR/2N (SN-12N-1 + SN-22N-2+...+S020).
The basic theory of the R-2R ladder network is actually quite simple. Current flowing through any input resistor (2R) encounters two possible paths at the far end. The effective resistances of both paths are the same (also 2R), so the incoming current splits equally along both paths. The half-current that flows back towards lower orders of magnitude does not reach the op amp, and therefore has no effect on the output voltage. The half that takes the path towards the op amp along the ladder can affect the output.
The most significant bit (marked "8" in the figure) sends half of its current toward the op amp, so that half of the input current flows through that final 2R resistance and generates a voltage drop across it. This voltage drop (from bit "8" only) will be one-third of the logic 1 voltage level, or 5/3 = 1.667 volts. This is amplified by the op amp, as controlled by the feedback and input resistors connected to the "-" input. For the components shown, this gain will be 3 (see the page on non-inverting amplifiers). With a gain of 3, the amplifier output voltage for the "8" input will be 5/3 × 3 = 5 volts.
The current from the "4" input will split in half in the same way. Then, the half going towards the op amp will encounter the junction from the "8" input. Again, this current "sees" two equal-resistance paths of 2R each, so it will split in half again. Thus, only a quarter of the current from the "4" will reach the op amp. Similarly, only 1/8 of the current from the "2" input will reach the op amp and be counted. This continues backwards for as many inputs as there are on the R-2R ladder structure.
The maximum output voltage from this circuit will be one step of the least significant bit below 10 volts. Thus, an 8-bit ladder can produce output voltages up to 9.961 volts (255/256 × 10 volts). This is fine for many applications. If you have an application that requires a 0-9 volt output from a BCD input, you can easily scale the output upwards using an amplifier with a gain of 1.6 (8/5).
Vo =   VR/2N (SN-12N-1 + SN-22N S020).

14. Why ADC ? Digital Signal Processing is more popular
Chap 0
Why ADC ?
Digital Signal Processing is more popular
Easy to implement, modify, …
Low cost
Data from real world are typically Analog
Needs conversion system
from raw measurements to digital data
Consists of
Amplifier, Filters
Sample and Hold Circuit, Multiplexer
ADC

15. ADC Essentials Basic I/O Relationship ADC is Rationing System
Chap 0
n bits ADC
Number of discrete output level : 2n
Quantum
LSB size
Q = LSB = FS / 2n
Quantization Error
1/2 LSB
Reduced by increasing n
ADC Essentials
Basic I/O Relationship
ADC is Rationing System
x = Analog input /
Reference
Fraction: 0 ~ 1

16. Converter Errors Hard to remove Integral Linearity Error Offset Error
Chap 0
Converter Errors
Integral Linearity Error
Differential Linearity Error
Nonlinear Error
Hard to remove
Offset Error
Gain Error
Can be eliminated by initial adjustments

17. Terminologies Converter Resolution
Chap 0
Terminologies
Converter Resolution
The smallest change required in the analog input of an ADC to change its output code by one level
Converter Accuracy
The difference between the actual input voltage and the full-scale weighted equivalent of the binary output code
Maximum sum of all converter errors including quantization error
Conversion Time
Required time (tc) before the converter can provide valid output data
Converter Throughput Rate
The number of times the input signal can be sampled maintaining full accuracy
Inverse of the total time required for one successful conversion
Inverse of Conversion time if No S/H(Sample and Hold) circuit is used

18. Analog Input Signal Typical Input Range
Chap 0
Analog Input Signal
Typically, Differential or Single-ended input signal of a single polarity
Typical Input Range
0 ~ 10V and 0 ~ 5V
If Actual input signal does not span Full Input range
Some of the converter output code never used
Waste of converter dynamic range
Greater relative effects of the converter errors on output
Matching input signal and input range
Prescaling input signal using OP Amp
In a final stage of preconditioning circuit
By proportionally scaling down the reference signal
If reference signal is adjustable

19. Outputs and Analog Reference Signal
Chap 0
Outputs and Analog Reference Signal
I/O of typical ADC
ADC output
Number of bits
8 and 12 bits are typical
10, 14, 16 bits also available
Typically natural binary
BCD (3½ BCD)
For digital panel meter, and digital multimeter
Errors in reference signal
From
Initial Adjustment
Drift with time and temperature
Cause
Gain error in Transfer characteristics
To realize full accuracy of ADC
Precise and stable reference is crucial
Typically, precision IC voltage reference is used
5ppm/C ~ 100ppm/C

20. Control Signals HBE / LBE Start BUSY / EOC From CPU
Chap 0
Control Signals
HBE / LBE
From CPU
To read Output word after EOC
HBE
High Byte Enable
LBE
Low Byte Enable
Start
From CPU
Initiate the conversion process
BUSY / EOC
To CPU
Conversion is in progress
0=Busy: In progress
1=EOC: End of Conversion

21. A/D Conversion Techniques
Chap 0
A/D Conversion Techniques
Counter or Tracking ADC
Successive Approximation ADC
Most Commonly Used
Dual Slop Integrating ADC
Voltage to Frequency ADC
Parallel or Flash ADC
Fast Conversion

22. Counter Type ADC Operation Reset and Start Counter Block diagram
Chap 0
Operation
Reset and Start Counter
DAC convert Digital output of Counter to Analog signal
Compare Analog input and Output of DAC
Vi < VDAC
Continue counting
Vi = VDAC
Stop counting
Digital Output = Output of Counter
Disadvantage
Conversion time is varied
2n Clock Period for Full Scale input
Block diagram
Waveform

23. Counter Type ADC Operation Reset and Start Counter Block diagram
Chap 0
Operation
Reset and Start Counter
DAC convert Digital output of Counter to Analog signal
Compare Analog input and Output of DAC
Vi < VDAC
Continue counting
Vi = VDAC
Stop counting
Digital Output = Output of Counter
Disadvantage
Conversion time is varied
2n Clock Period for Full Scale input
Block diagram
Waveform

24. Tracking Type ADC Tracking or Servo Type
Chap 0
Tracking Type ADC
Tracking or Servo Type
Using Up/Down Counter to track input signal continuously
For slow varying input
Can be used as S/H circuit
By stopping desired instant
Digital Output
Long Hold Time
Disabling UP (Down) control, Converter generate
Minimum (Maximum) value reached by input signal over a given period

25. Successive Approximation ADC
Chap 0
Successive Approximation ADC
Most Commonly used in medium to high speed Converters
Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved
SAR(Successive Approximation Register) holds the current binary value
Block Diagram

26. Successive Approximation ADC
Chap 0
Successive Approximation ADC
Circuit waveform
Logic Flow
Conversion Time
n clock for n-bit ADC
Fixed conversion time
Serial Output is easily generated
Bit decision are made in serial order

27. Dual Slope Integrating ADC
Chap 0
Excellent Noise Rejection
High frequency noise cancelled out by integration
Proper T1 eliminates line noise
Easy to obtain good resolution
Low Speed
If T1 = 60Hz, converter throughput rate < 30 samples/s
Operation
Integrate
Reset and integrate
Thus 
Applications
DPM(Digital Panel Meter), DMM(Digital Multimeter), …

28. Voltage to Frequency ADC
Chap 0
Voltage to Frequency ADC
VFC (Voltage to Frequency Converter)
Convert analog input voltage to train of pulses
Counter
Generates Digital output by counting pulses over a fixed interval of time
Low Speed
Good Noise Immunity
High resolution
For slow varying signal
With long conversion time
Applicable to remote data sensing in noisy environments
Digital transmission over a long distance

29. Parallel or Flash ADC Very High speed conversion
Chap 0
Parallel or Flash ADC
Very High speed conversion
Up to 100MHz for 8 bit resolution
Video, Radar, Digital Oscilloscope
Single Step Conversion
2n –1 comparator
Precision Resistive Network
Encoder
Resolution is limited
Large number of comparator in IC