1. Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf
DDRIII BASED General Purpose FIFO on Virtex-6 FPGA ML605 board PART A presentation
Students:
Oleg Korenev
Eugene Reznik
Supervisor:
Rolf Hilgendorf
Semester: spring 2012

2. Content Project overview Specifications Part A goals Memory on ml605
AXI4
Part A overview
Part B goals and Workflow
Timeline

3. Project Overview
Design and implementation of General Purpose FIFO IP core which allows usage of external memory (DDR3) as FIFO storage on Xilinx FPGA device
Design and implement generic IP core of FIFO
Design and implement GUI generator of IP core on PC
Create sample design with implemented IP core

4. Specifications Hardware Software
Xilinx Virtex-6 ML605 FPGA Evaluation Kit
DDR III memory
Ethernet interface
PC with Ethernet interface
Software
ISE Design Suite Logic Edition Version 14.3
Modelsim
Wireshark
Winpcap library

5. Our goals part a Gain experience in hardware development
(VHDL environment)
Explore and expertise FPGA work environment
Create design with configurable
word size
FIFO depth
Achieve best performance
Minimize usage of FPGA resources
Make our world a better place

6. MEMORY on ml605 DDR3 memory Capacity: 512MB
Max theoretical bandwidth: 800MT/s*64bit = 6.4GB/sec
Xilinx provides us with DDR3 controller which has AXI Memory Mapped interface
AXI bus data width up to 1024 bit
256 bit for max memory performance, assuming bus works with 200Mhz

7. 4AXI
Xilinx provides us with AXI4 Memory Mapped bus, which is a standard bus used in modern ARM SoC.
Features
Separate Address/Control and Data Phases
burst-based transactions with only start address issued
separate read and write data channels

8. General purpose Fifo AXI4 Interface CONTROLLER Native Fifo Interface
FIFO TO MEMORY
MEMORY TO FIFO
F I F O
F I F O
Native Fifo Interface

9. General purpose Fifo
interface
AXI4
Native FIFO
GP FIFO

10. part a overview general purpose Fifo
Interface
GP FIFO has native FIFO interface
Word size can be 32, 64, 128, 256, 512, 1024 bit
Utilizes DDR3 memory through AXI interconnect
Depth is limited only by available RAM memory on DDR3
Internal architecture
Internal FIFO-To-Memory controller
Internal Memory-To-FIFO controller
Internal Bypass controller
Arbitration between GP FIFOs is managed by AXI interconnect

11. Example DESIGN Block Diagram
DDR3
HOST STORAGE
LOGIC STORAGE
USER STORAGE
MEMORY CONTROLLER
AXI4 BUS (INTERCONNECT)
General Purpose Fifo
General Purpose Fifo
MAC Module
MAC Controller
HOST
Example Design

12. part a overview example design
Interface
Utilizes Ethernet MAC level of communication
Software has simple and intuitive interface
Software handles all the data transmission in between host and GP FIFO
Internal architecture
MAC module
GP FIFO
Simple example of a logic which uses GP FIFO
MAC can potentially provide us with a considerably high speed of data transmission, the bottleneck is software - driver performance

13. Part a overview conclusion
Our design meets the requirements of the project.
GP FIFO is fast limited only by interconnect bus available bandwidth
GP FIFO has potentially configurable depth and word size
GP FIFO is simple, utilizes small amount of resources on the board
GP FIFO gives you another easy way to pass big chunks of data from one module to another. Our example design provides you with efficient communication in between a host and the board.

14. Our goals part b Generalize our GP FIFO
Simulate and test all the possible configurations and their exceptional case
Make possible optimizations
Close timing on each configuration
Develop software generator of GP FIFO IP core
Write detailed manual for IP core and for it’s generator

15. Timeline Task 2 weeks 3 weeks Duration Generalize GP FIFO
16/6
9/6
2/6
26/5
19/5
12/5
5/5
28/4
21/4
14/4
7/4
Duration
Task
2 weeks
Generalize GP FIFO
Optimizations
3 weeks
Simulation and Testing
Close Timing
Develop IP core generator
Write manual