1. Photonic Networks on Chip Yiğit Kültür CMPE 511 – Computer Architecture Term Paper Presentation 27/11/2008

2. Contents  Introduction  Architecture Overview  Network Design  Analysis and Comparison  Conclusion

3. Introduction Multi-Core Architectures  Local processing frequencies reached fundamental performance limits: Further speed increase leads to tighter bounds on the logic coherently accessed on chip Associated power dissipation increases in an exponential fashion

4. Introduction Multi-Core Architectures  As a result processor manufacturers are introducing products based on multi-core architectures Aim is to optimize performance-per-watt by operating multiple parallel processors at lower clock frequencies

5. Introduction Multi-Core Architectures  AMD Opteron  Intel Montecito  Sun Niagara  IBM Cell  Power5

6. Introduction Emergence of a Key Bottleneck  Within the next few years, performance gains will come from increases in the number of processor cores per chip Global intrachip communications infrastructure will appear as a key bottleneck  Challange is to realize Enormous bandwidth capacity Low latency Power efficiency

7. Introduction Low-latency high-bandwidth: How?  Packet-switched networks Made of carefully engineered links Represent a shared medium that is highly scalable Provide enough bandwidth  But... Communication infrastructure is the major power consumer Power dissipation budget limit will be achieved

8. Introduction Photonic Technology  Photonic interconnection networks Low power dissipation independent of capacity Ultra-high throughput Minimal access latencies  Why less power? Once a photonic path is established, the data is transmitted end to end without the need for repeating, regeneration and buffering

9. Introduction Photonic Technology  Is photonic technology cheap enough? Since 2006, high-speed optical communications directly between silicon die are possible at a price-performance point competitive with traditional electrical interconnects

10. Contents  Introduction  Architecture Overview  Network Design  Analysis and Comparison  Conclusion

11. Architecture Overview Phonotonic NoC  Hybrid Approach Photonic interconnection network  Transmits high-bandwidth messages Electronic control network  Topologically identical to the photonic network  Controls the photonic network with small control messages

12. Architecture Overview Phonotonic NoC  Before transmitting a photonic message, an electronic control packet (path-setup packet) is routed in the electronic network acquires and sets up a photonic path for the message  Photonic message is transmitted without buffering once the path is acquired

13. Architecture Overview Photonic NoC  Main advantage of photonic paths is bit-rate transparency Photonic switches switch on or off once per message Energy dissipation does not depend on the bit-rate  whereas Traditional CMOS routers switch with every bit of transmitted data

14. Architecture Overview Photonic NoC  Another advantage is low loss in optical waveguides Power dissipated on a photonic link is completely independent of the transmission distance No matter if 2 cores are 2mm or 2cm apart

15. Architecture Overview Photonic NoC  2X2 photonic switching elements Capable of switching messages in a sub nanosecond switching time  Switches are arranged as a 2D matrix and organized in groups of four Each group is controlled by an electronic router to construct a 4X4 switch  Convenient for planar 2D topologies such as mesh and torus

16. Architecture Overview Photonic NoC  Each node includes a network gateway to serve as a photonic network interface Electronic/Optical (E/O) and Optical/Electronic (O/E) conversions Clock synchronization and recovery Serialization/deserialization  Wavelength division multiplexing is used at network gateways to provide larger data capacity Optical equivalent of using parallel wires

17. Architecture Overview Life of a Packet on Photonic NoC  Write operation from a processor in Node A to a memory in Node B 1.A path-setup packet is sent on the electronic control network  Includes information on the destination address of Node B and additional control information such as priority and flow id 2.Path-setup packet is routed in the electronic control network  Reserves the photonic switches along the path  At every router in the path, the next hop is decided according to the routing algorithm used 3.Path-setup packet reaches the destination Photonic path is reserved A fast light pulse is sent on the photonic path from Node B to Node A to indicate that the path is reserved

18. Architecture Overview Life of a Packet on Photonic NoC 4.The photonic message starts from Node A follows path from switch to switch until it reaches Node B 5.Message transmission completed 6.Path-teardown packet is sent from Node B to Node A on the electronic control network to release the path 7.Photonic message is checked for errors and a small acknowledgement packet is sent from Node B to Node A on the electronic control network

19. Contents  Introduction  Architecture Overview  Network Design  Analysis and Comparison  Conclusion

20. Network Design Building Blocks  Broadband Photonic Switching Element (PSE)  Based on a ring senator structure  Switch is a waveguide intersection positioned between two ring resonators  OFF State  Resonant frequency of the rings is different from the wavelength on which the optical data stream is modulated  Light passes through uninterrupted  ON State  Electrical current is injected to contracts surrounding the rings so that resonance of the rings shift  Light gets in the resonance and it is coupled into the rings making a right angle turn

21. Network Design Building Blocks  Broadband Photonic Switching Element (PSE)  Fast  30 ps switching time  Small  12 μm ring diameter  Low power consumption  <0.5 mW (ON)  ~0(OFF)

22. Network Design Building Blocks  PSEs are interconnected by silicon waveguides which carry photonic signals  PSEs are organized as groups of four  Electronic Router controls the quadruple, forming a 4X4 switch  Electronic Router is connected to the network with metal lines  Control packets are received in the electronic router, processed and sent to the next hop while PSEs are switched ON and OFF accordingly  Once a control packet completes the whole path, a chain of arranged PSEs are ready to transmit the photonic message  Small size  70 μm X 70 μm

23. Network Design Building Blocks  4X4 Switch is blocking  Constructing a nonblocking 4X4 switch requires an extremely complex structure Negative impact on the area Optical signal integrity  U-turns are forbidden to limit blocking

24. Network Design Topology  The communication requirements for a chip multiprocessor are best served by a 2D regular topology such as mesh and torus  A regular 2D topology requires 5X5 switches Too complex to implement using photonic technology  How to construct the topology with 4X4 switches? Use a folded torus topology as a base Add access points for the gateways  Facilitate injection and ejection without interference with the through traffic  Avoid blocking between injected and ejected traffic which may be caused by the switches’ internal blocking

25. Network Design Topology

26.  Avoid internal blocking by a set of injection-ejection rules: Injected messages make a turn at the gateway switch, according to their destination and enter the torus network through an injection switch Messages are ejected from the torus network when they arrive to the ejection switch associated with their final destination

27. Network Design Topology

28. Network Design Routing  Each message is encoded with two intermediate and a final address, encapsulated within one another  Routing: 1.1st intermediate address directs the message to the injection switch 2.Message is routed on the torus using plain XY dimension order routing to the 2nd intermediate address which is the ejection switch 3.Final address directs the message to the destination gateway

29. Network Design Flow Control  Flow control technique greatly differs from common fully electronic NoCs Electronic control packets are exchanged to acquire photonic paths Data are only transmitted with a very high bandwidth once the path is acquired Path setup latency >> Transmission latency  Control messages are very small and do not require large resources in terms of additional circuitry or power

30. Contents  Introduction  Architecture Overview  Network Design  Analysis and Comparison  Conclusion

31. Analysis and Comparison Power Dissipation  Case Study Setup 16-node CMP where each processor requires  BW peak = 1024 Gb/s  BW avg = 800 Gb/s Traffic driven by the processors is assumed to be uniform Both networks use a mesh topology and XY dimension order routing

32. Analysis and Comparison Power Dissipation  Reference Electronic Network 4X4 mesh, where each router is integrated in one processor tile PW=765W  Photonic Network 8X8 photonic mesh 256 photonic switching elements organized as 64 4X4 switches PW=30W(96% less power dissipation)

33. Contents  Introduction  Architecture Overview  Network Design  Analysis and Comparison  Conclusion

34. Conclusion  The advantages of photonic medium High transmission bandwidth Low power consumption  Recent (i.e. since 2006) advances make photonic technology practical for NoCs Fabrication of silicon photonic devices Integration of photonic devices in CMOS electronic circuits  Next generation of NoCs will possibly use photonic technology

35. References  On the Design of a Photonic Network-on-Chip Assaf Shacham, Keren Bergman, Luca P. Carloni First International Symposium on Networks-on-Chip (NOCS'07), pp. 53-64, 2007  Photonic Networks-on-Chip: Opportunities and Challenges Michele Petracca, Keren Bergman, Luca P. Carloni IEEE International Symposium on Circuits and Systems 2008 (ISCAS 2008), pp. 2789-2792, May 2008  The Case for Low-Power Photonic Networks on Chip Assaf Shacham, Keren Bergman, Luca P. Carloni Proceedings of the 44th Annual Conference on Design Automation, pp. 132-135, 2007  Maximizing GFLOPS-per-Watt: High-Bandwidth, Low Power Photonic On-Chip Networks Shacham, K Bergman, LP Carloni IBM P=ac2 Conference, October 2006