1. 3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection Workflow: Fabricate VICTR IC on 3D multiproject run 3/15(?) IC wafers dedicated to Ziptronix bonding Test chip functionality on non-DBI wafers Fabricate mating sensors at BNL >6 sensor wafers devoted to Ziptronix – yield of 2 with thinned Ics and 2 without Mate 3D wafer to handle at Ziptronix Ship to Tezzaron to reveal vias DBI processing of sensor and 3D IC wafer at Ziptronix Bond 3D chips to sensor wafer Dice 1

2. 3D Bonding/Tiling Process 2 R. Lipton May 8, 20092 Will be used for bonding Tezzaron 3D ICs to sensors

3. 3 Tezzaron 3D Processs Tezzaron (Naperville) has developed a 3D process utilizing CMOS wafers from a commercial IC foundry with cu-cu bonding and “standard” thinning and lithography Wafers with “vias first” are made as a process option at Chartered Semiconductor in Singapore. Wafers are bonded, thinned and topside processed in Singapore by Tezzaron Bond pads Bump bond pads Commercial (10 6 8” wafers), well characterized 0.13 micron process - avoids issues seen with MIT/OKI Bonding performed at 40 PSI and about 375 degrees C. Bonding done with improved EVG chuck 3 sigma alignment = 1 um Missing bond connections = 0.1 PPM CPU/Memory stack CMOS Sensor FPGA 6 microns

4. 4 Fermilab Tezzaron Multiproject Run Fermilab is organizing a multiproject run in the Tezzaron Process with a two-tier 3D wafer 17 institutions contributing Process can include MAPS option Designs include: Convert MIT LL VIP2a 3D design to the Tezzaron/Chartered process (VIP2b) - Fermilab ILC Convert 2D MAPS device design for ILC to 3D design where PMOS devices are placed on the tier without sensing diodes – Italy ILC CMOS pixels with one tier used as a sensitive volume and the second containing electronics. - France Convert the current 0.25 um ATLAS pixel electronics to a 3D structure with separate analog and digital tiers in the Chartered 0.13 um process. – France/US sLHC X-ray imaging/timing chip - Fermilab/BNL/Poland 3D chip with structures to test feasibility of a 3D integrated stacked trigger layer. - Fermilab sLHC 1 st wafer WB/BB pad TSV Inter-tier bond pads

5. 3D Doublet Layer Construction 5 5 Readout IC wafer with TSV from foundry Sensor DBI bond Oxide bond diced ROIC to sensor Wafer. Flip, thin to expose TSV Sensor Contact lithography provides Access to topside pads for vertical data path Sensor Thin to expose TSV Interposer Test, assemble module with interposer Sensor Bump Bond module Sensor

6. VICTR- Vertically Integrated CMS TRigger Chip 6 VICTR Front end from ATLAS 3D FEI4

7. VICTR Assembly 7 Z side 1 mm stripsPhi side 5 mm strips

8. DBI Process (W. Bair, Ziptronix) 8

9. DBI Test Devices at FNAL Demonstration of technology with wafers we had “on hand” BTeV FPiX 2.1 ROICs - 22 x 128 array of 50 x 400 micron pixels. 0.25 micron TSMC CMOS - 8” wafers MIT - LL 300 micron thick sensor wafers which had a matching pixel layout - 6” wafers Sensor “chips” were bonded to 8” ROIC wafers, then thinned to 100 microns Ohmic contact through trench or In-Ga eutectic 9 9.9mm

10. 10 Tezzaron MPW frame – each circuit contains right and left tiers after bonding VICTR VIP VIPIC

11. 11 8 mm VICTR Bottom sensor 1 mm strips VICTR will be DBI bonded to bottom sensor, top tier exposed Bottom sensor connected to top of VICTR through interposer Chips spaced apart to allow 1500 microns from guard to cut edge Top sensor 5mm strips VIPIC sensor VIP sensor Sensor Wafer

12. DBI Stack 12

13. Details of Layout 13 VICTR chip pads Redistributed pads in seed metal Seed metal traces Alignment targets

14. Details of Layout 14 pad TSV array Seed metal trace 2x2 DBI interconnect

15. Short Strip Pad 15 TSV Strip implant Sensor metalization Sensor implant via Seed metal DBI metal Sensor oxide opening Chip pad for testing

16. Long strip Pads 16 106 micron opening

17. Status 3D multiproject designs submitted to Chartered Discussions about space needed for Chartered test structures so processing had not started as of last week Sensor layout complete – discussion of design with BNL Sep. 22 Order placed with Ziptronix for DBI work Layout of associated DBI metal continuing. 17