1. ELECTRONIC CIRCUITS- I

2. DC Biasing Circuits
The ac operation of an amplifier depends on the initial dc values of IB, IC, and VCE.
By varying IB around an initial dc value, IC and VCE are made to vary around their initial dc values.
DC biasing is a static operation since it deals with setting a fixed (steady) level of current (through the device) with a desired fixed voltage drop across the device.

3. Purpose of the DC biasing circuit
To turn the device “ON”
To place it in operation in the region of its characteristic where the device operates most linearly, i.e. to set up the initial dc values of IB, IC, and VCE

4. Voltage-Divider Bias
The voltage – divider (or potentiometer) bias circuit is by far the most commonly used.
RB1, RB2
 voltage-divider to set the value of VB , IB , C3
 to short circuit ac signals to ground, while not effect the DC operating (or biasing) of a circuit
(RE  stabilizes the ac signals)
 Bypass Capacitor

5. Graphical DC Bias Analysis

6. DC Load Line The straight line is know as the DC load line
Its significance is that regardless of the behavior of the transistor, the collector current IC and the collector-emitter voltage VCE must always lie on the load line, depends ONLY on the VCC, RC and RE
(i.e. The dc load line is a graph that represents all the possible combinations of IC and VCE for a given amplifier. For every possible value of IC, and amplifier will have a corresponding value of VCE.)
It must be true at the same time as the transistor characteristic. Solve two condition using simultaneous equation
 graphically  Q-point !!
What is IC(sat) and VCE(off) ?

7. Q-Point (Static Operation Point)
When a transistor does not have an ac input, it will have specific dc values of IC and VCE.
These values correspond to a specific point on the dc load line. This point is called the Q-point.
The letter Q corresponds to the word (Latent) quiescent, meaning at rest.
A quiescent amplifier is one that has no ac signal applied and therefore has constant dc values of IC and VCE.

8. Q-Point (Static Operation Point)
The intersection of the dc bias value of IB with the dc load line determines the Q-point.
It is desirable to have the Q-point centered on the load line. Why?
When a circuit is designed to have a centered Q-point, the amplifier is said to be midpoint biased.
Midpoint biasing allows optimum ac operation of the amplifier.

9. DC Biasing + AC signal
When an ac signal is applied to the base of the transistor, IC and VCE will both vary around their Q-point values.
When the Q-point is centered, IC and VCE can both make the maximum possible transitions above and below their initial dc values.
When the Q-point is above the center on the load line, the input signal may cause the transistor to saturate. When this happens, a part of the output signal will be clipped off.
When the Q-point is below midpoint on the load line, the input signal may cause the transistor to cutoff. This can also cause a portion of the output signal to be clipped.

10. DC Biasing + AC signal

11. DC and AC Equivalent Circuits
Bias Circuit
DC equivalent circuit
AC equivalent circuit

12. AC Load Line
The ac load line of a given amplifier will not follow the plot of the dc load line.
This is due to the dc load of an amplifier is different from the ac load.

13. AC Load Line What does the ac load line tell you?
The ac load line is used to tell you the maximum possible output voltage swing for a given common-emitter amplifier.
In other words, the ac load line will tell you the maximum possible peak-to-peak output voltage (Vpp) from a given amplifier.
This maximum Vpp is referred to as the compliance of the amplifier.
(AC Saturation Current Ic(sat) , AC Cutoff Voltage VCE(off) )

14. AC Saturation Current and AC Cutoff Voltage

15. Amplifier Compliance
The ac load line is used to tell the maximum possible output voltage swing for a given common-emitter amplifier. In another words, the ac load line will tell the maximum possible peak-to-peak output voltage (VPP) from a given amplifier. This maximum VPP is referred to as the compliance of the amplifier.
The compliance of an amplifier is found by determine the maximum possible of IC and VCE from their respective values of ICQ and VCEQ.

16. Maximum Possible Compliance

17. Compliance
The maximum possible transition for VCE is equal to the difference between VCE(off) and VCEQ. Since this transition is equal to ICQrC, the maximum peak output voltage from the amplifier is equal to ICQ rC. Two times this value will give the maximum peak-to-peak transition of the output voltage:
VPP = the output compliance, in peak-to-peak voltage
ICQ = the quiescent value of IC
rC = the ac load resistance in the circuit
VPP = 2ICQrC
(A)

18. Compliance
When IC = IC(sat)­, VCE is ideally equal to 0V. When I­C = ICQ, VCE is at VCEQ. Note that when IC makes its maximum possible transition (from ICQ to IC(sat)), the output voltage changes by an amount equal to VCEQ. Thus the maximum peak-to-peak transition would be equal to twice this value:
Equation (A) sets the limit in terms of VCE(off). If the value obtained by this equation is exceed, the output voltage will try to exceed VCE(off), which is not possible. This is called cutoff clipping, because the output voltage is clipped off at the value of VCE(off).
Equation (B) sets of the limit in terms of IC(sat). If the value obtained by this equation is exceed, the output will experience saturation clipping.
(B)
VPP = 2VCEQ

19. Cutoff and Saturation Clipping
When determining the output compliance for a given amplifier, solve both equation (A) and (B). The lower of the two results is the compliance of the amplifier.

20. Example
For the voltage-divider bias amplifier shown in the figure, what is the ac and dc load line. Determine the maximum output compliance.

21. Transistor Bias Circuits

22. Objectives
Discuss the concept of dc biasing of a transistor for linear operation
Analyze voltage-divider bias, base bias, and collector-feedback bias circuits.
Basic troubleshooting for transistor bias circuits

23. Introduction
For the transistor to properly operate it must be biased. There are several methods to establish the DC operating point. We will discuss some of the methods used for biasing transistors as well as troubleshooting methods used for transistor bias circuits.

24. The DC Operating Point
The goal of amplification in most cases is to increase the amplitude of an ac signal without altering it.
Fig 5-1a, b, & c

25. The DC Operating Point
For a transistor circuit to amplify it must be properly biased with dc voltages. The dc operating point between saturation and cutoff is called the Q-point. The goal is to set the Q-point such that that it does not go into saturation or cutoff when an a ac signal is applied.
Fig 5-2a & Fig 5-4

26. The DC Operating Point
Recall that the collector characteristic curves graphically show the relationship of collector current and VCE for different base currents. With the dc load line superimposed across the collector curves for this particular transistor we see that 30 mA of collector current is best for maximum amplification, giving equal amount above and below the Q-point. Note that this is three different scenarios of collector current being viewed simultaneously.
Slope of the dc load line?
Fig 5-2a & Fig 5-4

27. The DC Operating Point
With a good Q-point established, let’s look at the effect a superimposed ac voltage has on the circuit. Note the collector current swings do not exceed the limits of operation(saturation and cutoff). However, as you might already know, applying too much ac voltage to the base would result in driving the collector current into saturation or cutoff resulting in a distorted or clipped waveform. (Example 5-1)
Fig 5-5 circuit and load line w/signals

28. Voltage-Divider Bias
Voltage-divider bias is the most widely used type of bias circuit. Only one power supply is needed and voltage-divider bias is more stable( independent) than other bias types. For this reason it will be the primary focus for study.
Fig 5-9 Voltage-Div. Bias

29. Voltage-Divider Bias
Apply your knowledge of voltage-dividers to understand how R1 and R2 are used to provide the needed voltage to point A(base). The resistance to ground from the base is not significant enough to consider in most cases. Remember, the basic operation of the transistor has not changed.
Fig 5-9 Voltage-Div. Bias

30. Voltage-Divider Bias
In the case where base to ground resistance(input resistance) is low enough to consider, we can determine it by the simplified equation RIN(base) = DCRE
We can view the voltage at point A of the circuit in two ways, with or without the input resistance(point A to ground) considered.
Fig 5-10a & b

31. Voltage-Divider Bias
For this circuit we will not take the input resistance into consideration. Essentially we are determining the voltage across R2(VB) by the proportional method.
VB = (R2/R1 + R2)VCC
Fig 5-9 Voltage-Div. Bias

32. Voltage-Divider Bias
We now take the known base voltage and subtract VBE to find out what is dropped across RE. Knowing the voltage across RE we can apply Ohm’s law to determine the current in the collector-emitter side of the circuit. Remember the current in the base-emitter circuit is much smaller, so much in fact we can for all practical purposes we say that IE approximately equals IC.
IE≈ IC
Fig 5-9 Voltage-Div. Bias

33. Voltage-Divider Bias
Although we have used npn transistors for most of this discussion, there is basically no difference in its operation with exception to biasing polarities. Analysis for each part of the circuit is no different than npn transistors.
Fig 5-16

34. Base Bias
This type of circuit is very unstable since its  changes with temperature and collector current. Base biasing circuits are mainly limited to switching applications.
Fig 5-19 Base bias circuit

35. Emitter Bias
This type of circuit is independent of  making it as stable as the voltage-divider type. The drawback is that it requires two power supplies.
Two key equations for analysis of this type of bias circuit are shown below. With these two currents known we can apply Ohm’s law and Kirchhoff's law to solve for the voltages.
Fig 5-21a npn emitter bias
IB ≈ IE/
IC ≈ IE ≈( -VEE-VBE)/(RE + RB/DC)

36. Collector-Feedback Bias
Collector-feedback bias is kept stable with negative feedback, although it is not as stable as voltage-divider or emitter. With increases of IC, less voltage is applied to the base. With less IB ,IC comes down as well. The two key formulas are shown below.
Fig 5-23 collector feedback
IB = (VC - VBE)/RB
IC = (VCC - VBE)/(RC + RB/DC)

37. Summary
The purpose of biasing is to establish a stable operating point (Q-point).
The Q-point is the best point for operation of a transistor for a given collector current.
The dc load line helps to establish the Q-point for a given collector current.
The linear region of a transistor is the region of operation within saturation and cutoff.

38. Stability Factor

39. Operating Regions Region of operation E – B junction C – B Cut off
Reverse Biased
Active
Forward Biased
Saturation

40. Ic Active Region Cut-off Region Vce Saturation Region Ib = 60μA
Ic = 10mA
Ib = 50μA
Ic = 8mA
Ib = 40μA
Ic = 6mA
Ib = 30μA
Ic = 4mA
Cut-off Region
Ib = 20μA
Ic = 2mA
0 V
24 V
Vce

41. Typical junction voltages
Transistor
Vce sat
Vbe sat
Vbe active
Vbe cut-in
Vbe cut-off Si
0.2 V
0.8 V
0.7 V
0.5 V
0 V Ge
0.1 V
0.3 V
-0.1 V
In the saturation region Ic >  Ib
For active region Vce > Vce(sat)

42. Ib = 31 A Ic=3.1mA Vce = 3.8 V Active
Problem
Rb = 300 K
Calculate Ib, Ic & Vce if  = 100 for the Silicon transistor. Find the region of operation
Hint
Vbe = 0.7 V Rb
300 K Ic
Vcc = 10 V Rc
2 K
Answer
Ib = 31 A Ic=3.1mA Vce = 3.8 V Active

43. Leakage current Io = 2 A at 250 C
Vbb -5 V
Vcc 10 V
Problem
Leakage current Io = 2 A at 250 C
Calculate Rb, if the Ge transistor remains in cut-off at 750 C
Hints
Leakage current doubles for every 100 C
I’o = Io . 2i/10
i = t2 – t1
Vbe(cut-off) = -0.1V Rc Rb
5.6 K
270 K Io
Answer
Rb = 76.6 K

44. Vbb -1 V
Vcc 10 V
Problem
If Vbb = 1 V, Rb = 50 K, upto what temperature, the transistor will remain in cut-off ? (Room temp. = 250 C
Hints
Find Io’
I’o = Io . 2i/10
i = t2 – t1
Find t2 Rc Io Rb
5.6 K
50 K
Answer
t2 = C

45. Show that the transistor is in saturation region Hints
+Vcc 10 V
Problem
Show that the transistor is in saturation region
Hints
In saturation Ic is not equal to  Ib
Vbe(sat) = 0.8 V
Ie = Ib + Ic
Find Ib & Ic Ib Ic
100K 2K
 100 1K Ie
Answer
Ib = 58.9 A
Ic = 3.24mA

46. Common Base Configuration-
Vbe _ + E B Ie Ic Ib
Vcb C
Input
Output
Here the input is applied at the Emitter & the output taken from the Collector
In this arrangement Base is common to the input & output
This is called Common Base configuration

47. Common Base ConfigurationRe Rc
Rb1
Rb2
Vcc Ie Ic
Input
Output Re Rc Ib _ _ + +
input
output
Vee
Vcc
The circuit can be re-drawn as shown, with input at Emitter & output at Collector
Vb is obtained using Rb1 & Rb2
This is called potential divider arrangement

48. Common Emitter Configuration_ + Ie Ic Ib
Vee
Vcc Re Rc
Rb1
Rb2
Vcc
Input
Output E C B
Input
Output
The circuit has been re-configured with input at Base & output at Collector
The Emitter is common to input & output
This is called Common Emitter configuration

49. Reverse Saturation current Ico
Vee _ +
Vcc
When Emitter is open, the base & collector act as a reverse biased diode
Since CB junction is reverse biased there will not be any Ic
However, there will be a current due to the minority charge carriers
This is called Reverse Saturation Current Ico

50. Reverse Collector Saturation current Icbo
Vee _ +
Icbo
Vcc Ie
Icbo is the leakage current that flows at the collector due to the minority charge carriers, in the common base mode
 Is the current gain in the CB mode

51. Reverse Collector Saturation current Iceo
Vee _ +
Iceo
Vcc Ie
Iceo is the leakage current that flows at the collector due to the minority charge carriers, in the common emitter mode
 Is the current gain in the CE mode

52. Ic = .Ie + Icbo = (Ib + Ic) + Icbo Ic (1- ) = Ib + Icbo 1 -  = Ic
Since  = 1
1 - 
+1 Ic
Icbo
(+1) +
 Ib =
i.e. Ic =  Ib + Iceo
where Iceo
= (+1) Icbo

53. Stability Temperature & Current gain variation may change the Q point
Stability refers to the design that prevents any change in the Q point
Temperature effect
When the temperature increases it results in the production of more charge carriers
This increases the forward bias of the transistor and Ib increases

54. Temperature effect
When the temperature increases it results in the production of more charge carriers
This increases the minority charge carrier and hence the leakage current as
Iceo = (+1) Icbo
Icbo doubles for every 100 C
As Ic =  Ib + Icbo
The increase in the temperature increases Ic
This in turn increases the power dissipation and again more heat is produced

55. Thermal Runaway This increases the power dissipation
This results in more heat
Again the charge carrier increases
The whole process repeats
Ultimately Ic may become too large and burn the transistor
This is called Thermal Runaway

56. Change in Vbe Vbe changes @ 25 mV per degree Celcius Ib depends on Vbe
Ic depends on Ib
Hence Ic changes with temperature
This shifts the operating point

57. Change in  The current gain  also depends on temperature
As Ic =  Ib, Ic varies with temperature
This shifts the Q point
Thermal stability should ensure that in spite of temperature change, the selected Vce, Ic & Power max do not change

58. Techniques Stabilization technique
Resistive biasing circuits change Ib suitably and keep Ic constant
Compensation technique
Temperature sensitive devices such as diodes, thermistors & transistors are used to provide suitable compensation and retain the operating point without shifting

59. Stability Factor
It indicates the degree of change in the operating point due to variation in temperature
There are 3 stability factors corresponding to the 3 variables – Ico, Vbe &  S
Ic
Ico =
Vbe,  constant
The stability factor should be as minimum as possible S’
Ic
Vbe =
Ico,  constant
S’’
Ic  =
Ico, Vbe constant

60. Stability Factor S Ic =  Ib + Iceo =  Ib + (I +  ) Icbo
i.e. Ic = Ib + (I +  ) Icbo
i.e. 1 = 
+ (I +  )
Ib
Ic
Icbo
i.e 
Ib
Ic
= (I +  )
Icbo
i.e.
Icbo
Ic =
( I +  )
1 - 
Ib
( I +  )
1 - 
Ib
Ic =
S =
Icbo
Ic

61. Design of biasing system

62. Fixed Bias Circuit
When Ib flows through Rb, there will be a voltage drop across Rb
Vb = Vcc – (Ib x Rb)
Ib = (Vcc – Vb) / Rb
= Vcc / Rb (approx)
Supply voltage Vcc is fixed
Hence once Rb is chosen Ib is also fixed
Hence the name Fixed bias circuit Ib
Vcc
Vbe Rb

63. When collector current Ic flows through Collector load resistor Rc, there will be a voltage drop across Rc
Vc = Vcc – (Ic x Rc)
Or, Vc < Vcc
Or, Ic < Vcc / Rc
In case Ic > Vcc / Rc, then the operating point lies in the saturation region
Vcc Ic Rc Ib Rb
Vce
Vbe

64. Problem
Design a fixed biased circuit using a silicon transistor having
 = 100
Vcc = 10 V
Vce = 5 V
Ic = 5 mA
Answer: Rc = 1 K Rb = 186 K

65. Problem A fixed bias circuit has  = 100 @ 250 C &  = 125 @ 750 C
Vcc = 12 V
Rb = 100 K
Rc = 600 
Determine % change in Q point values over the temperature range
Answer: %change in Ic = + 25%
%change in Vc = %

66. Stability Factor S For Fixed Bias Circuit Ic Ico S = = ( I +  )
Vbe,  constant S = =
( I +  )
1 - 
Ib
Ic
For the fixed Bias Circuit Ib = Vcc / Rb
Ib
Ic
. . .
= 0
S =
( I +  )
1 - (0)
. . .
S = 1 + 
. . .

67. Stability Factor S’ S’ = For Fixed Bias Circuit Ic =  Ib + Iceo Ic
Vbe =
Ico,  constant
=  Ib + ( + 1) Icbo
= 
Vcc - Vbe Rb
+ ( + 1) Icbo = -
+ ( + 1) Icbo Rb
 Vcc
 Vbe
. . . +
Ib
Vbe = Rb  _
S = -  / Rb
. . .

68. Stability Factor S’’ For Fixed Bias Circuit Ic = Ib + Iceo S’’   =
Ico, Vbe constant
= Ib + (+1)Icbo
= 
Vcc - Vbe Rb
+ ( + 1) Icbo = -
+ ( + 1) Icbo Rb
 Vcc
 Vbe
. . .
Ic  = -
+ Icbo Rb
Vcc
Vbe
= Ib + Icbo
= Ib (approx)
= Ic / 
S’’ = Ic / 
. . .

69. Vcc = 10 V Problem Rb = 100 K Rc = 2 K Vcc = 10 V Vce = 4 VIc
270 K
5.6 K
Vcc = 10 V Rc
2 K
4 V
Problem
Rb = 100 K
Rc = 2 K
Vcc = 10 V
Vce = 4 V
For this emitter grounded Fixed Bias circuit with Si transistor, find the stability factor S
Answer
S = 33.3

70. Advantages of fixed bias circuit
Simple circuit with minimum components
Operating point can be fixed conveniently in the active region, by selecting appropriate value for Rb
Hence fixed bias circuit provides flexibility in the design

71. Disadvantages of fixed bias circuit
Ic increases with temperature & there is no control over it
Hence there is poor thermal stability Ic =  Ib
Hence Ic depends on 
 may change from transistor to transistor
This will shift the operating point
Hence stabilization is very poor in fixed bias circuit

72. Collector to Base Bias Here Rb is connected between Base & Collector
Vcc
Collector to Base Bias
Ic+Ib
Here Rb is connected between Base & Collector
So, Ic & Ib flow through Rc Rc Ib Ic Rb
Vce

73. Equating the two equations Vcc – (Ic + Ib)Rc = (Ib Rb) + Vbe
Vce Rc Rb Ic
Vc = Vcc – (Ic + Ib) x Rc
Also, Vc = (Ib x Rb) + Vbe
Equating the two equations
Vcc – (Ic + Ib)Rc = (Ib Rb) + Vbe
Or, Ib(Rc + Rb) = Vcc – IcRc - Vbe
Ib =
Vcc – IcRc - Vbe
Rc + Rb
. . .
Ic =
( Vcc – IcRc – Vbe)
Rc + Rb
As Ic = Ib

74. Rb provides a feedback between Collector & Base Ib
Ic+Ib
Vcc
Vce Rc Rb
Rb provides a feedback between Collector & Base
If Ib or Ic tries to increase either due to temperature effect or due to variation in 
Voltage drop across Rc increases
This decreases Vce
This in turn reduces Ib, stabilizing the circuit

75. Problem Calculate the values of Ic & Vce for the given circuit Hint
 100
10 K
100 K
Problem
Calculate the values of Ic & Vce for the given circuit
Hint
Vcc = Rc(Ic + Ib) + Vce
Ic =  Ib
Vce = Rb Ib + Vbe
Vbe = 0.6
Answer
Ic = mA
Vce = 1.72 V

76. Problem
Design a collector to base circuit for the specified conditions:
Vcc = 15 V
Vce = 5 V
Ic = 5 mA
 = 100
Hint
Vcc = Rc(Ic + Ib) + Vce
Ic =  Ib
Vce = Rb Ib + Vbe
Answer
Rc = 1.98 mA Rb = 86 K

77. For Collector-Base Bias
Stability Factor S
For Collector-Base Bias S
Ic
Ico =
Vbe,  constant
Vcc = (Ib + Ic)Rc + IbRb + Vbe
=IcRc + Ib(Rc + Rb) + Vbe
0 = IcRc + Ib(Rc + Rb) + 0
after differentiation
or - IcRc = Ib(Rc + Rb)
Ib
Ic
. . .
-Rc
Rc + Rb =
S =
(I + )
1 - 
Ib
Ic =
(I + )
1 +  Rc
Rc + Rb

78. Stabilization with changes in 
If we design our circuit such that Rc >>Rb
Then S becomes independent of 
Hence  variation from transistor to transistor has no effect on the stability
S =
(1 + )
1 +  Rc
Rc + Rb
S =
1 + 
= 1

79. For Collector-Base Bias
Stability Factor S’
For Collector-Base Bias S’
Ic
Vbe =
Ico,  constant
Ib =
Vcc – IcRc - Vbe
Rc + Rb =
Vcc – IcRc - Vbe
Rc + Rb Ic 
Ic =
Rb + ( + 1) Rc
(Vcc – Vbe)  Ic +
Rc + Rb
IcRc
Vcc - Vbe = S’
Ic
Vbe =
Rc + Rb + Rc Ic 
(Rc + Rb)
Rc + Rb
Vcc - Vbe = =
Rb + ( + 1) Rc
- 

80. For Collector-Base Bias
Stability Factor S’’
For Collector-Base Bias
S’’
Ic
  =
Ico, Vbe constant
Vcc = (Ib + Ic)Rc + IbRb + Vbe
Vcc –Vbe = (Ib + Ic)Rc + IbRb
= Ib [(1 + )Rc +Rb]
Ib =
. . .
Vcc – Vbe
(1 + ) Rc + Rb
Ic =
. . .
( Vcc – Vbe)
(1 + ) Rc + Rb

81. . . .
Ic  =
[(1 + )Rc +Rb](Vcc –Vbe) - (Vcc –Vbe) Rc
[(1 + ) Rc + Rb]2
(Vcc –Vbe)[(1 + )Rc +Rb] - Rc
[(1 + ) Rc + Rb]2 =
(Vcc –Vbe)(Rc +Rb)
[(1 + ) Rc + Rb]2 = =
Vcc – Vbe
(1 + ) Rc + Rb
Rc + Rb x =
Ib(Rc + Rb)
(1 + ) Rc + Rb =
Ic(Rc + Rb)
[(1 + ) Rc + Rb]
. . .
S’’

82. If S is small, S’’ will also be small =
Ic(Rc + Rb)
[(1 + ) Rc + Rb]
S’’ =
(Rc + Rb)
(1 + ) Rc + Rb Ic 
1+  =
(1 + ) Rc + Rb Ic  1
1+ 
(Rc + Rb)
(1+ ) = Ic  S
1+ 
If S is small, S’’ will also be small
Hence if we provide stability against Ico variations, it will take care of  variation as well

83. Voltage Divider Bias Usually Vb is obtained using Rb & IbIc
270 K
5.6 K
Vcc Re Rc
Rb1
Rb2
Ib2 Ib Ie
Voltage Divider Bias
Usually Vb is obtained using Rb & Ib
Vb = Vc – Ib Rb
Thus Ib depends on Vb & Vb depends on Ib
To avoid this anomaly, two resistors Rb1 & Rb2 have been used
Rb1 & Rb2 act as Voltage Divider circuit giving Vb, irrespective of Ib

84. Rb1 is called Base Bias Resistor
Ib1 Ic
270 K
5.6 K
Vcc Re Rc
Rb1
Rb2
Ib2 Ib Ie
Rb1 is called Base Bias Resistor
Rb2 is called Base Bleeder Resistor
Vb is obtained based on the ratio of Rb1 and Rb2
Rb2
Vb = Vcc
Rb1 + Rb2

85. Rest of the equations remain the same Vc = Vcc – Ic Rc Vb = Ve + Vbe
Ib1 Ic
270 K
5.6 K
Vcc Re Rc
Rb1
Rb2
Ib2 Ib Ie
Rest of the equations remain the same
Vc = Vcc – Ic Rc
Vb = Ve + Vbe
Ve = Ie Re

86. For the Si transistor, if  is 100, find
+10 V
Problem
For the Si transistor, if  is 100, find
Vce & Ic
Hints
Find Vb, Ve, Ie, Ib
Answer
Ic = 5.2 mA
Vce = 2.16 V
Rb1 10 K Rc
1 K
Rb 2 5 K
Re 500

87. We can draw the Thevenin Equivalent Circuit for the base circuit
Ib1 Ic
270 K
5.6 K
Vcc Re Rc
Rb1
Rb2
Ib2 Ib Ic
5.6 K
Vcc Re Rc
Rb2 VT Ie R Ib
We can draw the Thevenin
Equivalent Circuit for the
base circuit
VT = Vb &
R = Rb1 II Rb2

88. For Voltage Divider Bias
Stability Factor S
For Voltage Divider Bias S
Ic
Ico =
Vbe,  constant
Vb = IbRb +Vbe + IeRe
= IbRb +Vbe + (Ib + Ic)Re
where Rb = Rb1 ll Rb2
Differentiating,
0 = IbRb IbRe + IcRe
i.e. Ib(Rb + Re) = - IcRe
S =
(I + )
1 - 
Ib
Ic =
(I + )
1 +  Re
Re + Rb
Ib
Ic
. . .
-Re
Rb + Re =

89. In the above equation, if Rb << Re, then S becomes 1
1 +  Re
Re + Rb
In the above equation, if Rb << Re, then S becomes 1
Rb = Rb1 ll Rb2
Hence either Rb1 or Rb2 must be << Re
Since Vb << Vcc, Rb2 is kept small wrt Rb1

90. If Rb-Re ratio is fixed, and if Rb >> Re, S increases with 
1 +  Re
Re + Rb
S =
(I + )
1 +  1
1 + Rb/Re
S =
(I + )
Re cannot be increased beyond a limit, as it will affect Ic and hence the Q point
If Rb-Re ratio is fixed, and if Rb >> Re, S increases with 
Thus stability decreases with increasing 

91. If Rb << Re, then S becomes independent of 
1 +  Re
Re + Rb
S =
(I + )
1 +  1
1 + Rb/Re
S = I
If Rb << Re, then S becomes independent of 
Stability factor S for Voltage Divider circuit is less compared to other circuits
Hence it is preferred over other circuits

92. For the Ge transistor, if  is 50, find Vce & Ic Find Ib,Vce, Ic & S
Problem
For the Ge transistor, if  is 50, find
Vce & Ic
Find Ib,Vce, Ic & S
Hint Vbe = 0.2 V
Answer
Ib = 76.3 uA
Vce = V
Ic = 3.81 mA
S = 25.14
Rb1 100 K
Rc 2 K
Rb2 5 K
Re 100

93. For the Si transistor, if  is 100 & Ic = 2 mA find
+20 V Re
Rc 2 K
Rb1 50 K
Rb2 5 K
Problem
For the Si transistor, if  is 100 & Ic = 2 mA find
Re,Vce, & S
Answer
Re = 149 
Vce = 7.7 V
S = 24.25

94. Problem
Design a voltage divider bias circuit for the given specifications:
Vcc = 12 V, Vce = 6 V, Ic = 1 mA, S = 20,  = 100 & Ve = 1 V
Answer:
Rb1= 150 K , Rb2 = 27 K, Rc = 4.7 K , Re = 1 K

95. For Voltage Divider Bias
Stability Factor S’
For Voltage Divider Bias
Vb = IbRb +Vbe + IeRe S’
Ic
Vbe =
Ico,  constant
= IbRb + Vbe + (Ib + Ic)Re
= Ib(Rb + Re) + Vbe + IcRe
= Ic /  (Rb +Re) + Vbe + IcRe
Or, Vb = Ic(Rb +Re) +  Vbe +  IcRe
= Ic[Rb +( + 1)Re] +  Vbe
0 = Ic[Rb +( + 1)Re] + Vbe
Differentiating,
Or, Vbe = - Ic [Rb +( + 1)Re] =
Rb + ( + 1) Re
-  S’
Ic
Vbe =

96. Stability Factor S’’ S’’   = Vb = IbRb +Vbe + IeRe
For Voltage Divider Bias
S’’
Ic
  =
Ico, Vbe constant
Vb = IbRb +Vbe + IeRe
= Ib(Rb + Re) + Vbe + IcRe
= Ic /  (Rb +Re) + Vbe + IcRe
Or, Vb = Ic(Rb +Re) +  Vbe +  IcRe
Or, (Vb – Vbe) = Ic(Rb +Re) +  IcRe
Differentiating,
(Vb – Vbe) = Ic(Rb +Re) + IcRe + Ic Re
(Vb – Vbe – IcRe) = Ic[Rb + Re+ Re]
. . .
Ic  =
S’’ =
Vb – Vbe - IcRe
Rb + Re(1+ )

97. Hence Rb / Re must be small to make S’’ smaller
Ic  =
S’’ =
Vb – Vbe - IcRe
Rb + Re(1+ ) =
Vb – Vbe - IeRe
Rb + Re(1+ )
As Ie = Ic =
Ib Rb
Rb + Re(1+ ) = Ib
1 +(Re/Rb)(1+ )
Hence Rb / Re must be small to make S’’ smaller

98. Self Bias In this circuit Re provides Self bias
Ib1 Ic
270 K
5.6 K
Vcc Re Rc
Rb1
Rb2
Ib2 Ib
Self Bias
In this circuit Re provides Self bias
When Ib or Ic tries to increase, Ie increases
This produces more drop across Re & increases Ve
This reduces Vbe which is Vb – Ve
This in turn reduces Ib and hence Ic
Thus Re provides a negative feed back and improves the stability

99. Bias Compensation
The biasing circuits seen so far provide stability of operating point for any change in Ico, Vbe or 
The collector- base bias & emitter bias circuits provide negative feedback & make the circuit stable, but the gain falls down
In such cases it is necessary to use compensation techniques

100. Diode Compensation Technique
Vcc
Here diode D has been connected as shown
It is given forward bias through Vdd
The diode D is identical to the BE junction of the transistor
The charge carriers will increase in the BE jn. due to temperature or other variations Rb Rc
270 K
5.6 K Rd Re - D
Vdd +

101. Rb
270 K
5.6 K
Vcc Rc Rd + - Re
Vdd D
Since diode D has similar properties, its charge carrier also increases, for any change in the parameters
Thus the increase in current in the BE junction is compensated by the current flow through the diode in the reverse direction.

102. Vcc
Another technique
Here the diode D has been connected in the bleeder path
When there is increase in current in the BE junction due to parameter changes, current through D also increases by the same amount
Ib1
Rb1 Rc
270 K
5.6 K D
Ib2 Re
Rb2

103. This increases Ib1, produces more drop across Rb1& reduces Vb
270 K
5.6 K
Vcc Rc Re
Rb2 D
This increases Ib1, produces more drop across Rb1& reduces Vb
As Vb decreases, Ib falls down
Thus the transistor currents are arrested and not allowed to increase
Thus diode D provides suitable compensation

104. Thermistor Compensation
270 K
5.6 K
Vcc Re Rc
Rb1
NTC Ib
Here a Negative Temperature Coefficient Resistor has been used
As temperature increases, its resistance decreases
This increases Ib1 & voltage drop across Rb1
This decreases Vb and hence Ib & Ic, thus keeping the circuit stable.
Ib1
Ib2

105. Sensitor Compensation
270 K
5.6 K
Vcc Re Rc
Rb2
PTC Ib
Here a Positive Temperature Coefficient Resistor has been used
As temperature increases, its resistance increases
This increases the voltage drop across Rb1(PTC)
This reduces Vb and Ib, thus keeping the circuit stable.
Rb1

106. Constant Current circuit
Vcc
Constant Current circuit
Re provides self bias
Vb is fixed depending on the ratio of Rb1 & Rb2 & the value of Vcc
Ve = Vb - Vbe
Vbe is fixed for a transistor
Hence Ve is fixed &
Ie = Ve / Re is also fixed
Hence it acts as a constant current circuit Rc
Rb1
5.6 K
Rb2 Re

107. For the given Si transistor find the constant current I
Problem
For the given Si transistor find the constant current I
Answer
I = 4.22 mA
Rb1 I
5.6 K
270 K
Rb2 4K7
Re 2K2
-20 V

108. FET Biasing

109. Introduction
For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation.
Nonlinear functions results in curves as obtained for transfer characteristic of a JFET.
Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach
The input of BJT and FET controlling variables are the current and the voltage levels respectively

110. Introduction JFETs differ from BJTs:
Nonlinear relationship between input (VGS) and output (ID)
JFETs are voltage controlled devices, whereas BJTs are current controlled

111. Introduction Common FET Biasing Circuits • JFET – Fixed – Bias
– Self-Bias
– Voltage-Divider Bias
• Depletion-Type MOSFET
• Enhancement-Type MOSFET
– Feedback Configuration

112. General Relationships
For all FETs:
For JFETs and Depletion-Type MOSFETs:
For Enhancement-Type MOSFETs:

113. Fixed-Bias Configuration
The configuration includes the ac levels Vi and Vo and the coupling capacitors.
The resistor is present to ensure that Vi appears at the input to the FET amplifier for the AC analysis.

114. Fixed-Bias Configuration
For the DC analysis,
Capacitors are open circuits and
The zero-volt drop across RG permits replacing RG by a short-circuit

115. Fixed-Bias Configuration
Investigating the input loop
IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configuration due to VGG is a fixed power supply so VGS is fixed
The resulting current,

116. Investigating the graphical approach.
Using below tables, we can draw the graph
VGS ID
IDSS
0.3VP
IDSS/2
0.5
IDSS/4 VP
0mA

117. The fixed level of VGS has been superimposed as a vertical line at
At any point on the vertical line, the level of VG is -VGG--- the level of ID must simply be determined on this vertical line.
The point where the two curves intersect is the common solution to the configuration – commonly referrers to as the quiescent or operating point.
The quiescent level of ID is determine by drawing a horizontal line from the Q-point to the vertical ID axis.

118. Output loop

119. Example
Determine VGSQ, IDQ, VDS, VD, VG, VS

120. Exercise
Determine IDQ, VGSQ, VDS, VD, VG and VS

121. Self Bias Configuration
The self-bias configuration eliminates the need for two dc supplies.
The controlling VGS is now determined by the voltage across the resistor RS

122. For the indicated input loop: Mathematical approach:
rearrange and solve.

123. Graphical approach Draw the device transfer characteristic
Draw the network load line
Use to draw straight line.
First point,
Second point, any point from ID = 0 to ID = IDSS. Choose
the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve.
The quiescent value for ID and VGS can then be determined and used to find the other quantities of interest.

125. For output loop
Apply KVL of output loop
Use ID = IS

127. Example
Determine VGSQ, IDQ,VDS,VS,VG and VD.

128. Example
Determine VGSQ, IDQ, VD,VG,VS and VDS.

129. Voltage-Divider Bias
The arrangement is the same as BJT but the DC analysis is different
In BJT, IB provide link to input and output circuit, in FET VGS does the same

130. Voltage-Divider Bias
The source VDD was separated into two equivalent sources to permit a further separation of the input and output regions of the network.
IG = 0A ,Kirchoff’s current law requires that IR1= IR2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of VG.

131. Voltage-Divider Bias VG can be found using the voltage divider rule :
Using Kirchoff’s Law on the input loop:
Rearranging and using ID =IS:
Again the Q point needs to be established by plotting a line that intersects the transfer curve.

132. Procedures for plotting
1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.

133. Once the quiescent values of IDQ and VGSQ are determined, the remaining network analysis can be found.
Output loop:

134. Effect of increasing values of RS

135. Example
Determine IDQ, VGSQ, VD, VS, VDS and VDG.

136. Example
Determine IDQ, VGSQ, VDS, VD and VS

137. Depletion-Type MOSFETs
Depletion-type MOSFET bias circuits are similar to JFETs. The only difference is that the depletion-Type MOSFETs can operate with positive values of VGS and with ID values that exceed IDSS.

138. Depletion-Type MOSFETs
The DC Analysis
Same as the FET calculations
Plotting the transfer characteristics of the device
Plotting the at a point that VGS exceeds the 0V or more positive values
Plotting point when VGS=0V and ID=0A
The intersection between Shockley characteristics and linear characteristics defined the Q-point of the MOSFET
The problem is that how long does the transfer characteristics have to be draw?
We have to analyze the input loop parameter relationship.
As RS become smaller, the linear characteristics will be in narrow slope therefore needs to consider the extend of transfer characteristics for example of voltage divider MOSFET,
The bigger values of VP the more positive values we should draw for the transfer characteristics

139. Analyzing the MOSFET circuit for DC analysis
How to analyze dc analysis for the shown network?
It is a …. Type network
Find VG or VGS
Draw the linear characteristics
Draw the transfer characteristics
Obtain VGSQ and IDQ from the graph intersection

140. 1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the voltage-divider bias circuit. These are the same calculations as used by a JFET circuit.

141. When RS change…the linear characteristics will change..
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the voltage-divider bias circuit. These are the same calculations as used by a JFET circuit.

142. Enhancement-Type MOSFET
The transfer characteristic for the enhancement-type MOSFET is very different from that of a simple JFET or the depletion-type MOSFET.

143. Transfer characteristic for E-MOSFET
and

144. Feedback Biasing Arrangement
IG =0A, therefore VRG = 0V
Therefore: VDS = VGS
Which makes

145. Feedback Biasing Q-Point
1. Plot the line using VGS = VDD, ID = 0 and ID = VDD / RD and VGS = 0
2. Plot the transfer curve using VGSTh , ID = 0 and VGS(on), ID(on); all given in the specification sheet.
3. Where the line and the transfer curve intersect is the Q-Point.
4. Using the value of ID at the Q-point, solve for the other variables in the bias circuit.

146. DC analysis step for Feedback Biasing Enhancement type MOSFET
Find k using the datasheet or specification given;
ex: VGS(ON),VGS(TH)
Plot transfer characteristics using the formula
ID=k(VGS – VT)2. Three point already defined that is ID(ON), VGS(ON) and VGS(TH)
Plot a point that is slightly greater than VGS
Plot the linear characteristics (network bias line)
The intersection defines the Q-point

147. Example
Determine IDQ and VDSQ for network below

148. Voltage-Divider Biasing
Again plot the line and the transfer curve to find the Q-point.
Using the following equations:
Input loop :
Output loop :

149. Voltage-Divider Bias Q-Point
Plot the line using VGS = VG = (R2VDD)/(R1 + R2), ID = 0 and ID = VG/RS and VGS = 0
Find k
3. Plot the transfer curve using VGSTh, ID = 0 and VGS(on), ID(on); all given in the specification sheet.
4. Where the line and the transfer curve intersect is the Q-Point.
5. Using the value of ID at the Q-point, solve for the other variables in the bias circuit.

150. Example
Determine IDQ and VGSQ and VDS for network below

151. = - + ) (

152. = - + ( )

153. Troubleshooting
N-channel VGSQ will be 0V or negative if properly checked
Level of VDS is ranging from 25%~75% of VDD. If 0V indicated, there’s problem
Check with the calculation between each terminal and ground. There must be a reading, RG will be excluded

154. P-Channel FETs
For p-channel FETs the same calculations and graphs are used, except that the voltage polarities and current directions are the opposite. The graphs will be mirrors of the n-channel graphs.

155. Practical Applications
• Voltage-Controlled Resistor
• JFET Voltmeter
• Timer Network
• Fiber Optic Circuitry
• MOSFET Relay Driver

156. Thanking You