1. Presenter : Ching-Hua Huang 2012/11/3 Implementation and Prototyping of a Complex Multi-Project System-on-a-Chip Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Wei-De Chien, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, and Chin-Long Wey National Chip Implementation Center (CIC), Hsinchu, Taiwan Department of Electrical Engineering, National Central University, Jhongli, Taiwan Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on National Sun Yat-sen University Embedded System Laboratory

2. A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip(MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoC projects sharing the common platform. The total silicon area is about 37.97mm 2 in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm 2 by implementing these projects separately, the results show that there are 91.42mm 2 silicon areas reduced by the MP-SoC platform. 2

3. 3 In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented. A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped-out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.

4. 4 What’s the problem  Many projects will be integrated in a SoC, namely MP-SoC. ◦ Reduced more area cost by use the MP-SoC.  In order to improve the robustness of MP-SoC design and verification ◦ A design flow was developed by CIC.

5. 5 Related work [This paper] A Novel Methodology for Multi-Project System-on-a-Chip [Popular methodology] Integrated a complex system into a single chip [3-5] [other paper reference] [1] Surviving the SoC Revolution: A Guide to Platformbased Designs [2] Multiprocessor SoC Platforms: A Component-Based Design Approach [3] A Case Study of the Novel Low-Cost SoC Silicon Prototyping Service for Taiwan Academia [4] Multi-Project System-on Chip (MPSoC): A Novel Test Vehicle for SoC Silicon Prototyping [5] PrSoC: Programmable System-on-Chip (SoC) for Silicon Prototyping [6] ARM RealView Versatile, ARM [other paper reference] STEAC: A platform for automatic SOC test [1] System level integration [2] Platform-based design Resolve the problem of high fabrication cost for SoC designs An automatic SOC integration platform “STEAC” was used to facilitate MP-SoC test integration [6] ARM™ RealView Versatile

6. 6 Proposed method  Virtual Prototyping ◦ A system modeling and HW/SW co-design virtual platform – ESL design methodology  Logical Implementation ◦ For IP’s development and verification  Rapid Prototyping ◦ ARM RealView Versatile ◦ A “CONCORD” platform  Physical Implementation ◦ The MP-SoC chip taped out to the foundry  Testing and Measurement ◦ Verigy 93000 ATE ◦ Customized development board

7. 7  The 1’st goal – CoSim ◦ All Verilog-based IP modules are packed with TLM interfaces and connected to SystemC-based platform in the simulation environment.  The 2’nd goal – Performance analyze ◦ These analysis functions help designers to detect the system bottlenecks.  Faster simulation speed ◦ About 100 times than pre-simulation. Verilog-based IP module

8. 8  STEAC ： SOC TEST AID CONSOLE  Synopsys VIP ： Synopsys Verification IP ◦ Provide the effective approach to verify circuit  It also can build the SoC platform rapidly. ◦ Provide the Functional Coverage and Monitoring  It can analyze this design whether conform to the specification. IP1 HDL coding Synthesis DFT/ATPG FPGA Synthesis HDL code IPn HDL coding … Synthesis DFT/ATPG … … STEAC Synthesis IEEE 1500 wrapper APR Netlist-> post-sim Netlist->pre-sim STEAC Test patterns

9. 9  ARM™ RealView Versatile ◦ The connection architecture is not enough  Support item  One core tile sub board  One FPGA tile sub board  CONCORD ◦ The bus architecture is designed into the main board ◦ The silicon IPs are designed into the sub boards  Support OpenRISC 、 ARM and LEON3 system

10. 10 Physical Implementation and Testing Chip Area4998x7598 um^2 Core Area4000x6600 um^2 Ring Width120um I/O Pad #485 ProcessTSMC 0.13um CMOS Process Critical Path Delay12.5ns(80MHz)@1.3V  TSMC 0.13um 1P8M  There are two testing environments are used in this MP-SoC. ◦ Verigy 93000 ATE ◦ Customized development board

11. 11  The silicon area can be significantly reduced. ◦ Saving approximately 70.6 % silicon area than fabricated individually.  A CONCORD platform ◦ Emulating the MP-SoC hardware before chip taping out. … … 10 IPs =129.39 … … v v v =37.97 10 IPs 91.42

12. 12  This paper is related to my tape-out working ◦ Virtual Prototyping  Co-Ware ◦ Logical Implementation  FPGA verification  Design compiler, IEEE 1500 wrapper, DFT and ATPG  Pre-layout simulation  SoC encounter, DRC and LVS check  Post-layout simulation ◦ Testing and Measurement  Verigy 93000 ATE  Customized development board  It provide the different design approaches ◦ STEAC : A platform for automatic SOC test ◦ CONCORD : A modulation SoC verification platform