1. Kamalapurkar Shounak Rajarshi Salil Joshi Rohan Bhavsar Sagar Pai Sandesh Low Latency Publisher-Subscriber Network for Stock Market Application Team WhiteWalkers

2. 2 Network Trader 1 (Subscriber) Trader 3 (Subscriber) Stock Exchange (Publisher) Intel Trader 2 (Subscriber) MicrosoftGoogleGoogle- Companies Subscriber Intel Subscriber 1 Microsoft Subscriber 3 Google Subscriber 2 Microsoft - Publisher- Subscriber Network SUBSCRIBER PACKET PUBLISHER PACKET

3. Physical Data Link Network Transport Session Presentation Application Publisher Trader # 1 Software based Deep Packet Inspection- DPI solution  High Latency  Not suitable for real-time applications  Unhappy Stock Brokers Software based DPI Update Destination Address Trader # 3 Trader # 2 Router Problems?

4. Publisher Physical Data Link Network Hardware based DPI solution DPI with Hardware Accelerators Update Destination Address Trader # 1 Trader # 3 Trader # 2 Router

5. Performance Evaluation *Performance Improvement in Hardware: > 10 X *Reference: Lockwood, “A low latency library in FPGA for High Frequency Trading” Our Method To Test:  Open Source DPI software Tool vs Our Processor Performance HWSW 10X

6. 6 Output Lookup Input queues Output queue High System Overview

7. Core 1 Input Arbiter Output Arbiter 7 Header- Checksum Core 2 Comparator Header- Checksum Comparator I am IDLE Which core is IDLE OK! Send to CORE1 BUSY Send to CORE 2 BUSY DONE! Processor Design

8. Source IP Destination IP Payload CAM KEYWORDS PROCESSOR New Destination Payload New Checksum Send Payload To Comparator Inspect the Data Send New IP Address To Checksum Gen Calculate New Checksum Send The Packet Hardware Accelerator Checksum Comparator New Checksum

9. Register File Data Mem PC 0 PC 1 Control Ins Mem Thread Select Example Instruction R1 R2 R1+R2 R3 ALU ADD R3,R2,R1 Hardware Accelerator Match Found! Update packet Special Load WordAdd Instruction

10. DescriptionCompletion Date Phase 1Single Core Multi-Threaded04/07 Phase 2Multi-core Multi-Threaded04/14 Phase 3Integration with Hardware Accelerators 05/05 Phase 4Testing and Debugging05/12 10 Project Schedule

11. Thank You! 11