1. Efficient Hardware dependant Software (HdS) Generation using SW Development Platforms Frédéric ROUSSEAU CASTNESS‘07 Computer Architectures and Software Tools for Numerical Embedded Scalable Systems Workshop & School Roma January 15-17th 2007

2. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 2 Summary  Context: Current multimedia applications require heterogeneous MPSoC  DSP + µC + sophisticated communication infrastructure Multiple software (SW) stacks  Multiple layers: Application SW code + HdS (Hardware dependent Software)  Specific architecture/application HdS to achieve efficiency  Problems: Classic SW development platforms do not fit: High level programming environment is not efficient to handle specific architecture capabilities HdS is Application/OS/architecture specific  Challenges: Efficient HdS generation Efficient and fast SW development platforms  Contribution: Specific HdS generation for Diopsis Specific SW development platforms for SW debug and validation

3. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 3 HdS generation  Hardware dependant Software (HdS) is composed of different layers Operating System (OS) Communication primitives Hardware Abstraction Layer (HAL) Application Programming Interface (API)  Why do we need HdS automatic generation ? Application/OS/Platform specific HdS  Difficulties Validation and debug (of each layer) HdS is used as an abstraction of HW by the application code  Requires HW and SW knowledge Task 1 HDS API Comm OS HAL API HAL Task 2 Task n HdS Tasks

4. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 4 GAP Classical HW/SW Interfaces Abstraction Models: The GAPS Hardware/Software discontinuity Virtual Prototype Correction cycle Functional specification Partition ning Software design Hardware design Integration ISA/RTL High Level App. model Early HW/SW integration Abstract HW/SW Interface Software development platform Fully implicit HW/SW Interface Fully explicit HW/SW Interface

5. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 5 SW Development Platforms & HdS Virtual architecture Transaction accurate architecture High level application model (tasks + mapping) HdS Library Virtual prototype HdS generation (TIMA)  High level application model System architecture(SA) model Implicit communication  Virtual architecture (VA) Final application code & HdS API Explicit communication Explicit mapping to execution subsystems Implicit execution models & task control  Transaction accurate architecture (TA) Explicit OS, specific I/O, HAL API Explicit communication and peripherals Abstract computation model of CPU  Virtual prototype Explicit execution models (CPU, communication) HdS implements com. API & task control over OS and architecture

6. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 6 SW Development Platforms & HdS Virtual architecture Transaction accurate architecture HdS generation High level application model (tasks + mapping) HdS Library Virtual prototype  High level application model System architecture(SA) model Implicit communication  Virtual architecture (VA) Final application code & HdS API Explicit communication Explicit mapping to execution subsystems Implicit execution models & task control  Transaction accurate architecture (TA) Explicit OS, specific I/O, HAL API Explicit communication and peripherals Abstract computation model of CPU  Virtual prototype Explicit execution models (CPU, communication) HdS implements com. API & task control over OS and architecture D940 Diopsis tile Abstraction SW development platform generation

7. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 7 Software design flow in SHAPES Virtual architecture Transaction accurate architecture HdS generation High level application model (tasks + mapping) HdS Library SW development platform generation D940 Diopsis tile Abstraction Virtual prototype (Aachen) Application mapping (ETH) Architecture

8. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 8 Detailed contributions  Abstraction of the RDT Diopsis Tile With the specific communication schemes At different abstraction levels (Virtual and Transaction levels)  Software development Platforms generation Debug and validation of the different SW stacks and layers Different abstraction levels  HdS Generation From a high level application model Using the specific communication schemes of Diopsis

9. TIMA Laboratory - Frédéric ROUSSEAU - CASTNESS’07 Roma January 17 th 9 Next presentations Virtual architecture Transaction accurate architecture High level application model (tasks + mapping) HdS Library Virtual prototype D940 Diopsis tile Abstraction SW development platform generation HdS generation  SW Development Platform generation Efficient SW Development Platform for Multimedia Applications by Katalin Popovici  HdS generation Software Code Generation from a Simulink Application Model by Xavier Guérin  Demo Application of Software Code Generation Flow from Simulink to Diopsis Platform by Katalin Popovici