1. Presented By Dwarakaprasad Ramamoorthy An Optimized Integrated QVCO for Use in a Clock Generator for a New Globally Asynchronous, Locally Synchronous (GALS) Design Methodology.

2. Overview Background Need for this new design methodology. Why GALS? What is novel in this design? Need for QVCO Design Strategy Simulations & Layout Conclusion

3. CLOCK GENERATOR Clock sin  u cos  u sin  t cos  t Phase Locked Loop Dual Sample & Hold Multiplier Init2! Done! Run CDA Multiplier Init1! SRFF1 SRFF2 sin  t  u) Ref [1]

4. Simple Phase Locked Loop Source: http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html

5. VCO Core Design Ref [4]

6. SIOS (Spiral Inductor On Silicon) Design Spiral Inductor Parameters Symbol QuantityValue D0D0 Outer area length320 µm D0D0 Outer area width320 µm WConductor width18 µm SConductor Spacing2 µm NNumber of turns6 WnWn Return path width18 µm LnLn Return path length120 µm LsLs Series inductance7.82 nH RsRs Series resistance6.24 Ω QQuality factor5 Q max Maximum quality factor10 f max Frequency at Q max 1.89 GHz SRFSelf resonating frequency4.33 GHz Ref [6], [8]

7. Inversion Mode (I-MOS) Varactor Design Ref [9]

8. Quadrature Generation Ref [12], [13]

9. QVCO Simulation Summary

10. QVCO Performance Summary Center frequency618 MHz – 687 MHz Tuning range10% Phase noise-190 dBc/Hz at 600 MHz Current consumption at 2.5 V power supply 8.4 mA Power consumption at 2.5 V power supply 21 mW TechnologyTSMC 0.25 µm, single-poly, five-metal, 2.5 V CMOS technology

11. QVCO Full Custom Layout

12. Conclusion A good compromise between area and overall power consumption was achieved. A prototype quadrature –G m LC-VCO for 650 MHz was designed in standard 0.25 µm, single-poly, five-metal, 2.5 V CMOS technology. A tuning range of 10% was obtained through the use of I-MOS varactors.

13. Conclusion (Contd.) SIOS achieving a Q of 5 were also created. Simulated worst-case phase noise is -190 dBc/Hz at 600 MHz. Occupies an area of 800 µm X 300 µm (0.24 mm 2 ). The designed VCO dissipates only 21 mW and operates from a single 2.5 V supply voltage.

14. Future Work Incorporate QVCO into PLL Design. Complete other Clock Generator Modules.

15. Presented By Dwarakaprasad Ramamoorthy An Optimized Integrated QVCO for Use in a Clock Generator for a New Globally Asynchronous, Locally Synchronous (GALS) Design Methodology.