1. Flip Chip And Underfills
                                                                 
Hemant Parate
Vikas Agarwal

2. Top: Flip Chip; Bottom: SMC
What is Flip Chip?
                            )                                    
Flip Chip Technology is an advanced from of surface mount technology, in which bare semiconductor chips are turned upside down, and hence called flip chip (i.e active face down), and bonded directly to a Printed circuit Board or Chip Carrier Substrate
Top: Flip Chip; Bottom: SMC

3. Why Flip Chip
To eliminate the expense, unreliability and low productivity of wirebonding
Wirebonding is peripheral and time consuming bond technique whereas flip chip progressed to area array and allow all I/O’s to be connected simultaneously which allow for high I/O counts at larger pitches and reduced die size
Self aligning chip’s bump pattern to corresponding substrate pad
Shortest possible leads, lowest inductance, highest frequency, best noise control, highest density, greater no of I/O’s, smallest device footprint, reduced cost

4. How They Are Made: Flow Chart Process
Main Steps:
Bumping
Bonding to Substrate
Underfill

5. UBM and solder bumps

6. Reasons for Using UBM
UBM is to a flip chip bump what a foundation is to a house
The final metal layer of most IC bond pads is aluminum
Aluminum is not a readily solderable surface, neither wettable nor bondable by most solders and get oxidized when expose to air which acts as an insulator
Adhesion Layer: Adhere to Al pad, the chip passivation, & low contact resistance
Barrier Layer: Diffusion barrier during soldering process
Wetting Layer: good wettability of solder material
Oxidation resistant Barrier: prevent oxidation of the surface

7. Solder Bumps Types of Solder Bump Formation Techniques: Evaporation
Electroplating
Printing
Stud Bumping
Direct Placement
The result of these methods may differ in bump size and spacing ("pitch"), solder components and composition, cost, manufacturing time, equipment required, assembly temperature, and UBM.

8. Evaporation Technique

9. Electroplating Technique

10. Printing Technique

11. Stud Bumping Creates conductive gold stud bumps on die bond pads
Connects to substrate with adhesive or ultrasonic assembly
No UBM required
Similar to “ball bonding” process used in wire bonding

12. In ball bonding, the tip of the gold bond wire is melted to form a sphere. The wire bonding tool presses this sphere against the aluminum bond pad, applying mechanical force, heat, and ultrasonic energy to create a metallic connection. The wire bonding tool next extends the gold wire to the connection pad on the board, substrate, or lead frame, and makes a "stitch" bond to that pad, finishing by breaking off the bond wire to begin another cycle.
For gold stud bumping, the first ball bond is made as described, but the wire is then broken close above the ball. The resulting gold ball, or "stud bump" remaining on the bond pad provides a permanent, reliable connection through the aluminum oxide to the underlying metal

13. Flip Chip Bonding
Thermocompression
Thermosonic
Adhesives

14. Thermocompression Bumps bonded to pads on substrate by force and heat
Process requires gold bumps on the chip and a correspondingly bondable surface (e.g. gold, aluminium)
The bonding temperature is
300 °C for gold bonding, to soften the material and increase the diffusion bonding process.
Bonding force is 1N for 80um bump

15. Thermosonic
Ultrasonic energy transferred to the bonding area from the pick-up tool through the back surface of the chip
Main benefit compared to
thermocompression is lower bonding temperature and shorter processing time
Damage may result from from excessive ultrasonic vibrations

16. Adhesives - isotropic and anisotropic
Ease of processing, low curing temp, elimination of need to clean after the bonding process
Isotropic conductive
adhesives are pastes of epoxy and conducting particle silver that assures conductivity in all direction
Anisotropically conductive adhesives are pastes of thermoplastics filled with metal coated polymer spheres that assures insulation in all direction before bonding and electrically conductivity in z-direction after bonding

17. Underfill
Non-Conductive adhesive joining surface of chip to substrate.
Protects bumps from moisture or other environmental hazards.
Provides mechanical strength to assembly.
CTE of silicon is 3 ppm/ °C and typical FR4 material is 17 ppm/ °C - large strain observed in solder bumps due to this thermal expansion mismatch
Compensates for this mismatch
-underfill mechanically locks together chip and substrate so differences in CTE do not break or damage electrical connection of bumps.
-Drawn under chip space by capillary action and heating C for viscosity.

18. Underfill Problems
Underfill process is biggest throughput bottleneck in flip chip today.
Dispensing challenges include:
Achieving complete and void-free flow under the die.
Dispensing around closely packed die
Avoiding contamination to other components.
Controlling flux residues.

19. Testing/Reliability
Testing required at various stages to ensure functionality.
Before solder balls are applied to chip.
After chip is attached to substrate.
After underfill is added and the whole package is complete
Reliability issues with solder ball cracking are tested by cycling the chips through temperature tests from around –50C to 150C.
-Some may include
-so there can be rework on ball attach before underfill is applied.
-to simulate turning the chip on and off during it’s lifetime
This finds when the chip breaks after so many cycles.
-at different manufacturing steps they also run resistance and continuity tests., because if you catch a failing part and throw it out of the batch you save money in the next step by not packaging a faulty part.

20. Widening availability of flip chip materials, equipment, and services
Advantages
Size
Performance
Flexibility
Reliability
Cost
Widening availability of flip chip materials, equipment, and services
               
               
Size:
Eliminating packages and bond wires reduces the required board area by up to 95%, and requires far less height. Weight can be less than 5% of packaged device weight. Flip chip is the simplest minimal package, smaller than Chip Scale Packages (CSP’s) because it is chip size.
Highest Performance:
Flip chip offers the highest speed electrical performance of any assembly method. Eliminating bond wires reduces the delaying inductance and capacitance of the connection by a factor of 10, and shortens the path by a factor of 25 to 100. The result is high speed off-chip interconnection.
Greatest I/O Flexibility:
Flip chip gives the greatest input/output connection flexibility. Wire bond connections are limited to the perimeter of the die, driving die sizes up as the number of connections increases. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Area connections also allow 3-D stacking of die and other components.
Most Rugged:
Flip chip is mechanically the most rugged interconnection method. Flip chips, when completed with an adhesive "underfill," are solid little blocks of cured epoxy. They have survived the laboratory equivalents of rocket liftoff and of artillery firing, as well as millions of cumulative total hours of actual use in computers and under automobile hoods
Lowest Cost:
Flip chip can be the lowest cost interconnection for high volume automated production, with costs below $0.01 per connection. This explains flip chip’s longevity in the cost-conscious automotive world, pervasiveness in low cost consumer watches, and growing popularity in smart cards, RF-ID cards, cellular telephones, and other cost-dominated applications.

21. Disadvantages Lack of standards for procedures due to limited adoption
Manufacturing issues are difficult
Visual verification of bump placement isn’t easy.
Thermal cycle fatigue of solder joints, especially if under fill isn’t used
Viscosity of under fill materials changes with time, therefore wicking process may vary over time of day and shifts
Most ordinary Pb solders have trace quantities of radioactive elements, which may cause soft errors in memory circuits
In fine pitch, solder flux becomes trapped and is very hard to clean. Leading to corrosion effects, gross solder voids, delaminations, etc.
BGA packages present test problems after board mounting with respect to ball integrity. Voids in the joints may lead to reliability issues down the road
X-ray scanning can be used to help this problem.

22. Future Market
Worldwide flip chip consumption is over 600,000 units per year.
Projected annual growth of nearly 50% per year.

23. Emerging Technologies in Flip Chip
Fast-flow, Snap-cure underfill process
Test boards and acoustic imaging of underfill voids.
Flip Chip pin Grid Array Packaging
Fluxless Solder bumping.
Many More in Research
Underfill
Bumping techniques and materials

24. Fast-Flow, Snap-cure Underfills
- with use of new underfill chemistrys which cure faster and stay in place we can combine the solder reflow and underfill cure process. This increases throughput by a large amount. But it is still under research.

25. Test boards and Acoustic Micro imaging
A 100 MHz acoustic image shows the condition of the cured underfill. The dark diagonal streaks and corner areas are filler particle aggregation; red features are voids in the underfill in areas of particle aggregation and over the 600 µm diameter uncovered vias near corners.
-underfill process want to study the flow of the fluid
-shape and size of filler particles are important
-uneven dispersal of filler cause nonuniform distribution of stress in cured epoxy.
-Topography of substrate surface has big impact on underfill flow. Features such as solder mask and uncovered vias can cause sudden changes in vertical dimension of the gap.
-acoustic image is reflected by internal interfaces that indicate two different materials properties. Finding voids etc.
-very-high freq. Ultrasound is pulsed and received by a scanning transducer. The Si die and underfill are transparent to ultrasound and return echoes from deeper in package.
-test board used with eight different substrate patgterns plus two reference patterns
-used to characterize different underfill materials for your process.
Small open via pattern->

26. Flip Chip Pin Grid Array Packaging (FCPGA)
Used in Intel Pentium 3
Pins inserted into a socket. Turned upside down so that the die or the part of the processor that makes up the computer chip is exposed on the top of the processor. By having the die exposed allows the thermal solution to be applied directly to the die, which allows for more efficient cooling of the chip.
-cross section of substrate
-Stackup The substrate is comprised of an FR-5 equivalent core with two resin build-up layers on each side. Both blind and buried vias are used to ease package routing.
Bump Pitch The flip-chip interconnects are built on an organic substrate with a solder bump pitch of 11 mils (279.4 µm).
Decoupling Capacitors Pin side decoupling capacitors were added to lower the power supply loop inductance.
Surface Mount Package Pins SMT pins were used to ease package routing. This was an improvement over through hole mounted pins. The use of SnSb solder to join the package and pins provided solder joint reliability through subsequent reflow operations.
Figure 1: Pin side view of the FCPGA package

27. Sources General trade articles Conferences Journal Articles
Electronic Packaging and Production, “Packaging’s Crystall Ball: The 2001 ITRS Roadmap”, Eric Bogatin, 3/1/2002
SMT Magazine, “Test Boards simplify Flip Chip Underfill Processing”, Karl-Friedrich Becker, March, 2001.
SMT Magazine, “Increased Yield and Reliability of the Flip Chip Process”, Brian J. Lewis, 2002.
Conferences
2000 Electronics Packaging Technology Conference, IEEE, “Flip Chip Pin Grid Array Packaging Technology”, Hwai Peng Yeoh.
Journal Articles
IEEE Transactions on Advanced Packaging, “Improved Thermal Fatique Reliability for Flip Chip Assemblies Using Redistribution Techniques”, Bart Vandevelde and Eric Beyne, Vol. 23, No.2, May 2000.

28. Sources cont… Books Web
Flip Chip Technologies, ed. John H. Lau, McGraw-Hill, 1996.
Silicon processing for the vlsi era (volume 1-process technology), S.Wolf/R.N. Tauber,Lattice Press, 2000.
Web