1. Group member: Zhaoxin Mamengduo Cfang Stanley The Implementation of Delta-Sigma Modulation in Digital-to-Analog Converter 1

2. Project Idea Motivation: EE 505 CMOS Data Conversion circuits During the process of digital-to-analog converting Use Delta-sigma modulator to push noise in music to high frequency band Use speaker/headphone as the low-pass filter to filtrate high frequency white noise 2

3. Top Level Components Delta-sigma modulation Delta-sigma modulation Low pass filter PCM(digital) In Serial Pulse Width Modulation (PWM,digital) Signal In Serial 3

4. Level-shifter for DVD Output Signal Output signal(from DVD) voltage: -0.5V~+0.5V Schmidt trigger: SN74LS14N 4 rheostat

5. Demo Film1 Play CD Film1 http://www.youtube.com/watch?v=582E_OXeVOU Film2 Input signal voltage shift Film2 http://www.youtube.com/watch?v=uBhcLwn46QM&fea ture=youtu.be Film3 Sleep mode Film3 http://www.youtube.com/watch?v=Q74URMVuhF8&fe ature=youtu.be 5

6. The Structure of DAC module 6

7. Input: PCM 7

8. The 3-stage Delta-sigma Modulation Y 1 ＝ X+(1 － Z -1 )Q Y 2 ＝－ Q 1 ＋（ 1 － Z － 1 )Q 2 Y 3 ＝（－ Q 2 ）＋ (1 － Z -1 )Q 3 Y ＝ X+ （ 1 － Z － 1 ) 3Q 3 PCM PWM 8

9. Eleven PWM Signals 9

10. Output: PWM PWM: digital signal but has analog info. 10

11. Matlab Simulation: Noise is pushed to higher frequencies 11

12. Using Filter to Cutoff Noise 12

13. One Order Noise Shaping Model Q ＝ Y － U U － Y ＝－ Q U ＝ X － Q 13

14. One Order Noise Shaping Model U (n) ＝ X (n) － Q (n-1) Q (n) ＝ Y (n) － U (n) Y (n) ＝ X (n) － Q (n － 1) ＋ Q (n) ＝ X (n) ＋ Q (n) － Q (n － 1) Q (n) － Q (n － 1) ＝（ 1 － Z － 1 ）Q Y ＝ X ＋（ 1 － Z － 1 ）Q 14

15. The 3-stage Delta-Sigma Modulation Y 1 ＝ X+(1 － Z -1 )Q Y 2 ＝－ Q 1 ＋（ 1 － Z － 1 )Q 2 Y 3 ＝（－ Q 2 ）＋ (1 － Z -1 )Q 3 Y ＝ X+ （ 1 － Z － 1 ) 3Q 3 15

16. Clock Synchronization with DVD Input signal(from DVD) is in serial: Need to decode SPDIF signal So need to synchronize clock with DVD 16

17. Clock Synchronization and Data Extraction 17

18. Clock Synchronization 44.1kHz frame rate×2 channel ×32 data×2 phase ＝ 5.6448MHz Keep detecting : temp1=temp2=temp3 & temp4=temp5=temp6 Then generate sampling clock @ center pulse 18

19. Clock Synchronization(cont.) 19

20. Data Extraction 20

21. Data Extraction(cont.) Keep detecting frame header 11100010 or 00011101 | 11100100 or 00011011 21

22. Sleep Mode(Power Saving) system 22

23. Volume Control Matlab verification Lower volume: right shift Larger volume: left shift Debounce module( real world) 23

24. Reference http://en.wikipedia.org/wiki/Delta-sigma_modulation http://www.cscamm.umd.edu/programs/ocq05/adams/ad ams_ocq05.pdf http://www.cscamm.umd.edu/programs/ocq05/adams/ad ams_ocq05.pdf http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.ht ml http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.ht ml http://www.intersil.com/data/an/an9504.pdf http://hephaestusaudio.com/media/2009/07/MASH- Delta-Sigma.pdf http://hephaestusaudio.com/media/2009/07/MASH- Delta-Sigma.pdf 24

25. Thank you! Q and A 25