2. May 8, 20012 USB 2.0 Technical Overview Brad Hosler USB Engineering Manager Intel Corporation

3. May 8, 20013 Conference Goal w Provide you with the information you need to build USB 2.0 products – USB 2.0 technical details – USB 2.0 Infrastructure – Building USB 2.0 devices – USB 2.0 Building Blocks

4. May 8, 20014 USB 2.0: Conference Agenda w Architecture Overview – Peripheral Development Enabling – Hi-speed power – Hi-speed performance w Microsoft SW Update w USB 2.0 Compliance and Logo Program w USB 2.0 Compliance Testing Single Track: Topics for Everyone

5. May 8, 20015 Split Track: Focused Topics USB 2.0: Technical Agenda w USB2 Specifications – Electricals – Protocol – Hubs w Power Management w Host Controller Spec – Compliance testing w Cable Testing w USB “On the Go” w USB2 Software – Writing Quality Drivers – HS Isoch Interface w Building USB2 Devices w Design Options w Transceiver Macrocell w Analyzers w Platform Design w BIOS considerations

6. May 8, 20016 Architecture Overview

7. May 8, 20017 USB 2.0: What Changed?? w Low level electricals for High Speed (HS) signaling – Much higher bit rate (480Mb/s) requires new transmitter/receiver w Hub changes for backward compatibility – Features limit bandwidth impact of Full Speed (FS) and Low Speed (LS) devices on HS devices – FS/LS devices consume a bit-rate equivalent of HS bandwidth Architecture Overview

8. May 8, 20018 USB 2.0: What Didn’t Change? w Same host/device model – Host is in charge – Devices are inexpensive w Same basic protocol – Token, data, handshake w Same device framework – Descriptors w Same software interfaces – USBDI Architecture Overview

9. May 8, 20019 w Same power distribution and consumption – 500ua suspend, 100ma unconfigured, 500ma configured w Same power management features – Suspend/resume model unchanged w Same topology management – Hub features to handle connect, disconnect, enable, disable, … w Same cables and connectors Continued Architecture Overview USB 2.0: What Didn’t Change?

10. May 8, 200110 System SW Client Driver USB 1.1 Hub USB 1.1 Device HS Hub USB 1.1 Hub USB 1.1 Device HS Device USB 2.0 Host Controller Controller Full/Low Speed High Speed Only (2 x 12Mb/s Capacity) Sample USB 2.0 Topology w Hub provides high-speed expansion (ala USB 1.1 hub) w Hub provides additional Full/Low speed bus(es) Architecture Overview

11. May 8, 200111 USB 2.0 Host Controller w Allows port functionality regardless of OS version – USB 1.1 OS will ‘just work’ as USB 1.1 ports w USB 1.1 HCs can go away over time – Replaced with integrated USB 2.0 Hub Architecture Overview USB 2.0 Host Controller (HC) Port 1 USB 1.1 USB 1.1HCs High-Speed Mode (Enhanced Interface) USB HC Port 1Port 2 Port Owner Control(s) Port 1Port 2 Port Routing Logic Port N HC Control Logic/Data Buffering Enhanced HC Control Logic Enhanced Data Buffering Port 2Port N

12. May 8, 200112 USB 2.0 Hub w Hub controller same as USB1.1 w Routing logic connects device to appropriate path TransactionTranslatorTransactionTranslator PortPort Routing Logic HS Signal Repeater Repeater HubControllerHubController PortPort PortPortPortPort High Speed only Full/LowSpeed Architecture Overview

13. May 8, 200113 Transaction Translator (TT) w TT handles low/full speed transactions – Driven with split transactions w Start-Split – Host tells Hub to initiate full/low speed transaction w Complete-Split – Host asks Hub for results of previous full/low speed transaction Architecture Overview

14. May 8, 200114 Bandwidth Usage w Low/full speed devices use bit-rate equivalent of USB2.0 bandwidth – 6Mbps classic camera (50% of classic) uses less than 2% of USB2.0 bandwidth (6Mbps/480Mbps) Architecture Overview

15. May 8, 200115 ISOCH IN through a TT HS Bus Full Speed Bus uSOF 1ms uSOF SOF SS SS = Start Split CS 125us CS = Complete Split Architecture Overview

16. May 8, 200116 Summary w Two major changes for USB 2.0 – Higher speed electricals – Transaction translator in USB2.0 hub w Backward compatibility – All Full/Low-speed devices continue to work – Has little impact on HS bandwidth Architecture Overview

17. May 8, 200117 Enabling Peripheral Development

18. May 8, 200118 USB 2.0 HC Cards w PCI and PCCard versions – Use NEC silicon – Full EHCI implementation w Available in retail – Frys, Circuit City, … – www.orangemicro.com, www.adaptec.com, … Peripheral Enabling

19. May 8, 200119 Driver Software w HC driver for Windows 2000 and Windows XP – Available at www.usb.org for member companies w Drivers provide full functionality – All high-speed transfer types – Full support for USB 2.0 hub transaction translator w Drivers are for development use only – Cannot be shipped with products Peripheral Enabling

20. May 8, 200120 Single Transaction Tool w Software application for generating individual high-speed transactions w Very useful for early device debug w Doesn’t require a device to enumerate w Any type of transaction can be generated – Including individual parts of Control transfers w Available at www.usb.org Peripheral Enabling

21. May 8, 200121 Transceiver Macrocell ASICASIC Serial Interface Engine Device Specific Logic Endpoint Logic … SIE Control Logic USB 2.0 Endpoint Logic Device Hardware USB 2.0 Transceiver Defines Standard Interface for Transceiver Macrocell w USB 2.0 Transceiver Macrocell Interface (UTMI) http://developer.intel.com/technology/usb/spec.htm w Broad Industry support w Discrete versions available Peripheral Enabling

22. May 8, 200122 VHDL (IP) Cores ASICASIC Serial Interface Engine Device Specific Logic Endpoint Logic … SIE Control Logic USB 2.0 Endpoint Logic Device Hardware USB 2.0 Transceiver Tran- sceiver Product Function USB 2.0 3rd Party VHDL Peripheral Enabling

23. May 8, 200123 Building Blocks w Microcontrollers – Cypress w Interface chips – Netchip w IDE/ATAPI bridges – In-System Design, NEC w ENET 10/100 Bridge – Kawasaki LSI w UTMI macro cells – Seiko-Epson, Kawasaki LSI w UTMI Transceivers – Lucent, Kawasaki LSI Peripheral Enabling

24. May 8, 200124 Bus Analyzers w Available now w Catalyst – http://www.catalyst-ent.com w CATC – http://www.catc.com w Crescent Heart – http://www.c-h-s.com w Data Transit – http://www.data-transit.com Peripheral Enabling

25. May 8, 200125 Peripheral Integration Lab w Integration lab at Intel’s Architecture Labs in Oregon – Multiple hosts and devices (interop testing) – Test equipment (scopes, analyzers, TDRs, etc.) – Expert help from HW and SW engineers – Compliance testing – Platforms and host controllers welcome too w Available to anyone planning on delivering USB 2.0 device in 2001 Peripheral Enabling

26. May 8, 200126 Hi-Speed Power Issues

27. May 8, 200127 Power Requirements w Suspended - ~2.5ma w Configured - 500ma w UnConfigured - 100ma w Examine each of these from a hi-speed device and infrastructure (host, hub, cable) perspective Hi-Speed Power

28. May 8, 200128 Suspend Current w Device: – Device is always in FS mode, HS clocks are off – Implementations should be similar to current solutions w Host/Hub: – Important for Instantly Available PCs – Dual-mode power supplies are sized to provide power to USB port when machine is ‘sleeping’ – ‘Don’t care’ for hubs and cables Hi-Speed Power

29. May 8, 200129 Configured Current w Device: – Hi-speed transceivers tend to consume more power – Less power available for device function w Host/Hub: – Power supplies sized to support this – Cable conductors sized for appropriate IR drop Hi-Speed Power

30. May 8, 200130 Unconfigured Current w Device: – Hi-speed transceiver can consume most of budget – Difficult to build bus-powered hi-speed devices w Host/Hub: – Important for bus-powered hubs u Four downstream ports at 100ma each – ‘Don’t care’ for hosts, self-powered hubs, and cables Hi-Speed Power

31. May 8, 200131 Issues w We like bus-powered devices – This is an essential characteristic for products w Is the 100ma limit really a problem? – Transmit/receive differences u Device is >99% receiving when unconfigured w Would increasing to 150ma be enough? – Impacts bus-powered hubs u Limited to two ports (300ma for ports, 200 for hub silicon) – Any other impacts? Comments/suggestions to electricals@usb.org Hi-Speed Power

32. May 8, 200132 Hi-Speed Detection Handshake

33. May 8, 200133 Downstream Ports w Port is driving RESET w Port must detect 2.5us ChirpK starting from 2.5us after asserting RESET until 7ms after asserting RESET Hi-Speed Handshake Device turns on HS termination Reset

34. May 8, 200134 Upstream Ports w Two cases: Reset from FS and reset from HS w Both cases – ChirpK must be at least 1ms in duration and must be complete within 7ms after RESET began w Reset from FS – Device must start ChirpK sometime between 2.5us and 6ms after detecting RESET w Reset from HS – After device sees SE0 for 3ms and reverts to FS terminations, then does ChirpK if there is still an SE0 Hi-Speed Handshake

35. May 8, 200135 Reset from HS Hi-Speed Handshake

36. May 8, 200136 Hi-Speed USB Performance

37. May 8, 200137 Mass Storage Performance w Standard IDE drive connected through different means ConnectionRead(MB/s)Write(MB/s) Seek Time (msec) USB 2.0 12.19.913.5 USB 1.1 0.920.8815.4 IDE same bus 2.12.014.2 IDE separate bus 15.113.612.3 Data provided by In System Design. Values measured with HD Tach 2.61, 30GB IBM drive, 333Mhz PIII system, 320MB RAM Hi-Speed USB Performance

38. May 8, 200138 Mass Storage Performance w Benchmark comparison of USB 2.0 high-speed USB drive with IDE drive BenchmarkPIO-3PIO-4UDMAUSB1 Business Disk WinMark 99 105%106%90%260% High-End Disk WinMark 99 155%154%95%534% Data provided by Quantum Corp. Hi-Speed USB Performance

39. May 8, 200139USB1IDEUSB2 ‘Rip’ an audio CD 15m 6m 40s 3m 15s Write an audio CD 24m 6m 10s 4m 20s CD/RW Performance w Time comparison for reading and writing an audio CD w Time to copy data CD: 6m 28s – USB2 to USB2 P4 system, 128MB, 1.3GHz. TDK 16/10/40 CDRW. In System IDE bridge. Hi-Speed USB Performance

40. May 8, 200140 Summary w Everything you need to develop USB2 products is available – Tools, host controllers, building blocks, analyzers w Building bus-powered high-speed products is difficult – Is a change to unconfigured power limit needed? w High-speed products deliver great performance – Comparable to ‘inside-the-box’ performance