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Copyright 2001, Agrawal & BushnellLecture 1 Introduction1 VLSI Testing Lecture 1: Introduction Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical.

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Presentation on theme: "Copyright 2001, Agrawal & BushnellLecture 1 Introduction1 VLSI Testing Lecture 1: Introduction Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical."— Presentation transcript:

1 Copyright 2001, Agrawal & BushnellLecture 1 Introduction1 VLSI Testing Lecture 1: Introduction Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal IIT Delhi, Aug 17, 2013, 10:00-11:00AM

2 Course Description Copyright 2001, Agrawal & BushnellLecture 1 Introduction2 This course is designed for the MTech program in VLSI at IIT, Delhi. It is patterned after a one- semester graduate-level course offered at Auburn University. A set of 17 lectures that include classroom exercises provide understanding of theoretical and practical aspects of VLSI testing. The course fulfills the needs of today’s industrial design environment, which demands knowledge of testing concepts of digital, memory, analog and radio frequency (RF) subsystems often implemented on a system-on-chip (SoC).

3 Outline n Lecture 1:Introduction (18*+2)* Number of slides n Lecture 2:Yield and quality (16+3) n Lecture 3:Fault modeling (20+2) n Lecture 4:Testability analysis (27) n Lecture 5:Logic simulation (15) n Lecture 6:Fault simulation (19) n Lecture 7:Combinational ATPG (24+3) n Lecture 8:Sequential ATPG (19+2) n Lecture 9:Delay test (26) n Lecture 10:Memory test (26) n Lecture 11:Analog test (27) n Lecture 12:Model-Based and Alternate Test (15) n Lecture 13:DFT and Scan (23+2) n Lecture 14:BIST (29) n Lecture 15:System diagnosis (21) n Lecture 16:RF Testing: Introduction, Gain Measurement (39) n Lecture 17:RF Testing: Intermodulation and Noise Measurements (34) Copyright 2001, Agrawal & BushnellLecture 1 Introduction3

4 Schedule n Aug 17, 2013 – 10AM-12PM Lectures 1 and 2 n Aug 19, 2013 – 2:30-4:30PM Lectures 3 and 4 n Aug 20, 2013 – 2:30-4:30PM Lectures 5 and 6 n Aug 21, 2013 – 2:30-4:30PM Lectures 7 and 8 n Aug 23, 2013 – 2:30-4:30AM Lectures 9 and 10 n Aug 24, 2013 – 10AM-12PM Lectures 11 and 12 n Aug 24, 2013 – Take-Home Exam assigned n Aug 26, 2013 – 2:30-4:30PM Lectures 13 and 14 n Aug 27, 2013 – 2:30-4:30PM Lectures 15 and 16 n Aug 28, 2013 – 2:30-4:30PM Lectures 17 n Aug 28, 2013 –Take-Home Exam due 4:30PM Copyright 2001, Agrawal & BushnellLecture 1 Introduction4

5 Copyright 2001, Agrawal & BushnellLecture 1 Introduction5 Introduction n VLSI realization process n Verification and test n Ideal and real tests n Costs of testing n Roles of testing n A modern VLSI device - system-on-a-chip n Testing Digital Memory Analog RF n Textbook n Problem to solve

6 Copyright 2001, Agrawal & BushnellLecture 1 Introduction6 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

7 Copyright 2001, Agrawal & BushnellLecture 1 Introduction7 Definitions n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

8 Copyright 2001, Agrawal & BushnellLecture 1 Introduction8 Verification vs. Test Verification n Verifies correctness of design. n Performed by simulation, hardware emulation, or formal methods. n Performed once prior to manufacturing. n Responsible for quality of design. Test n Verifies correctness of manufactured hardware. n Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware n Test application performed on every manufactured device. n Responsible for quality of devices.

9 Copyright 2001, Agrawal & BushnellLecture 1 Introduction9 Problems of Ideal Tests n Ideal tests detect all defects produced in the manufacturing process. n Ideal tests pass all functionally good devices. n Very large numbers and varieties of possible defects need to be tested. n Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

10 Copyright 2001, Agrawal & BushnellLecture 1 Introduction10 Real Tests n Based on analyzable fault models, which may not map on real defects. n Incomplete coverage of modeled faults due to high complexity. n Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. n Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

11 Copyright 2001, Agrawal & BushnellLecture 1 Introduction11 Testing as Filter Process Fabricated chips Good chips Defective chips Prob(good) = y Prob(bad) = 1- y Prob(pass test) = high Prob(fail test) = high Prob(fail test) = low Prob(pass test) = low Mostly good chips Mostly bad chips Tested chips

12 Copyright 2001, Agrawal & BushnellLecture 1 Introduction12 Costs of Testing n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead n Software processes of test Test generation and fault simulation Test programming and debugging n Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

13 Present and Future* Copyright 2001, Agrawal & BushnellLecture 1 Introduction13 * SIA Roadmap from www.siaonline.org, July 23, 2012www.siaonline.org

14 Copyright 2001, Agrawal & BushnellLecture 1 Introduction14 Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Logic block A Logic block B Primary inputs (PI) Primary outputs (PO) Test input Test output Int. bus Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks.

15 Copyright 2001, Agrawal & BushnellLecture 1 Introduction15 Cost of Manufacturing Test in 2000AD n 0.5-1.0GHz digital clock; analog instruments; 1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M n Annual running cost (five-year linear depreciation) = Depreciation (20%) + Maintenance (2%) + Operation ($0.5M) = $0.854M + $0.085M + $0.5M = $1.439M/year n Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

16 Copyright 2001, Agrawal & BushnellLecture 1 Introduction16 Roles of Testing n Detection: Determination whether or not the device under test (DUT) has some fault. n Diagnosis: Identification of a specific fault that is present on DUT. n Device characterization: Determination and correction of errors in design and/or test procedure. n Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

17 Copyright 2001, Agrawal & BushnellLecture 1 Introduction17 A Modern VLSI Device System-on-Chip (SOC) DSP core RAM ROM Inter- face logic Mixed- signal Codec Data terminal Transmission medium

18 Copyright 2001, Agrawal & BushnellLecture 1 Introduction18 Textbooks n Digital, memory and mixed-signal: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http://www.eng.auburn.edu/~vagrawal/BOOK/books.html n RF testing 1. J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and SiP Devices, Boston: Artech House, 2007. 2. B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey: Prentice Hall PTR, 1998. 3. K. B. Schaub and J. Kelly, Production Testing of RF and System- on-a-chip Devices for Wireless Communications, Boston: Artech House, 2004.

19 A Problem to Solve n Using the testing cost obtained in Slide 15, determine what is the component of test in the cost of a mixed-signal VLSI chip for the following data: Analog test time = 1.5 s Digital test clock = 200MHz Number of digital test vectors = 10 9 Chip yield = 70% Copyright 2001, Agrawal & BushnellLecture 1 Introduction19

20 Solution Copyright 2001, Agrawal & BushnellLecture 1 Introduction20 Assuming that one vector is applied per clock cycle during a digital test, the rate of test application is 200 million vectors per second. Therefore, Digital test time = (1000 × 10 6 )/(200 × 10 6 ) = 5 seconds Adding the analog test time, we get, Total test time = 1.5 + 5.0 = 6.5 seconds The testing cost for a 500 MHz, 1,024 pin tester was obtained as 4.56 cents in Slide 15. Thus, Cost of testing a chip = 6.5 × 4.56 = 29.64 cents The cost of testing bad chips should also be recovered from the price of good chips. Since the yield of good chips is 70%, we obtain Test cost per good chip = 29.64/0.7 ≈ 42 cents 42 cents should be included as the cost of testing while figuring out the price of chips.

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