1. Superscalar SMIPS Processor Andy Wright Leslie Maldonado

2. Project Goals N-way superscalar execution – Up to N instructions can be issued every cycle – N execution pipelines will share a single data memory IPC > 1 – Shows that superscalar execution is working

3. Background Data Hazards Control Hazards Structural Hazards – An instruction can’t be issued if it needs to use the same hardware as another instruction at the same time – Relevant for: Data Memory Redirect FIFO Coprocessor

4. System Overview

6. Instruction Memory Needs to be able to output N words 4 3 2 1 0 Normal Instruction Memory

7. Instruction Memory 12 8 4 0 13 9 5 1 14 10 6 2 15 11 7 3 Read from Address 0

8. Instruction Memory 12 8 4 0 13 9 5 1 14 10 6 2 15 11 7 3 Read from Address 0 01 2 3

9. Instruction Memory 12 8 4 0 13 9 5 1 14 10 6 2 15 11 7 3 Read from address 5 Unaligned accesses need permutations 85 6 7

10. Instruction Memory 12 8 4 0 13 9 5 1 14 10 6 2 15 11 7 3 85 6 7 56 7 8

11. Instruction Memory

12. Superscalar Fifo Needs to be able to enqueue N instruction per cycle Needs to be able to dequeue 1-N instructions per cycle Architecture similar to instruction memory

13. Superscalar Fifo

14. Scoreboard Keeps track of pending register writes to prevent RAW hazards – Scoreboards are used to prevent conflicts between instructions across clock cycles and within the same clock cycle Dispatch logic searches and writes to the scoreboard Writeback removes from the scoreboard – The order of these two operations depends on the type of registerfile

15. Scoreboard

17. Execution Pipelines Cores are given priorities between them Core 0 has earlier instructions than core 1 A mispredict in core I should kill instructions in cores > i

18. Execution Pipelines

19. Results (N=2)

20. Results (N=3) Didn’t get IPCs greater than 1, meaning this design was slower than the N=2 case. Why? – The branch predictor The branch predictor only predicts 1 out of every N instructions using the better branch predictor. The misprediction penalty is high, and the processor is paying the penalty more often for larger N’s

21. Structural Hazards in Bluespec Dispatch logic prevents two modules from needing to use the same hardware Bluespec compiler also checks for structural hazards, but is more aggressive. We had to create wrappers that would allow multiple modules to attempt to write to the same modules but only one actually gets to use it based on a fixed priority. If dispatch logic works, then the priority doesn’t matter since there will always be only one module write to it.

22. Conclusion We added N-way superscalar execution to the original SMIPS processor We saw IPC > 1 for every benchmarks on at least one processor for N=2 We tried N=3, but it suffered too much from misprediction