1. WP7&8 Progress Report ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR Objectives 2014 and current status

2. 2 ITS objectives for 2014 – WP7 and WP8 1.Finalization of OB geometry (with inputs from WP1 and WP2) and layout (with WP9 and WP10). Power Bus Flexible Printed Circuit 2 x 7 Pixel Chips Cold Plate Half-Stave Half-Stave Left Half-Stave Right Space Frame Half-Stave WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

3. 3 FPC extender  Study of the end of Stave services has started WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

4. 4 ITS objectives for 2014 – WP7 and WP8 2.Design, prototype and characterization of FPC Layout specs: -Size: 32.1 mm x 216 mm -Plated holes (~200 μm diameter) -Pads for FPC to FPC and FPC to PB interconnections test -tin soldering  short cables or SMD 0402 resistors, metallized holes -stack-up Cover-sheet 25 µm Copper 18 µm Kapton 75 µm WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

5. 5  Daisy-chain layout prototype Similar to the IB Delivery ongoing To be used for soldering tests 220,4 mm 30,1 mm  TDR-layout prototype 210,6 mm 30,1 mm WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

6. 6  Functioning layout prototype Main features 2 x Master chips Parallel data transmission Internal daisy chain: 4 data lines @ 80Mb/s (pins DATAIN[3:0] - DATAOUT[3:0]) 1 Clear To Send line (pins CTSO-CTSI) internal CLK and CRTL (pins CLK – CTRL): busy signal Differential CLK and CTRL (DCLKI – DCTRLI) from end-stave -> to each Master (traces on the 1 mm off the chips) 6 by-passing differential DATA lines from adjacent modules Module and chip Identification Geometry and Layout Differential lines: width = 100μm, spacing = 100μm, pitch between adjacent pairs = 300μm Pads for FPC to FPC and FPC to PB connection size to be defined WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

7. Chip Floorplan v2 (by Gianluca) OB FPC7 7WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

8. Functioning FPC routing 8WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

9. 9 ITS objectives for 2014 – WP7 and WP8 2.Design, prototype and characterization of Power Bus  Baseline for the prototype development: Al conductive layers Double layers: 2 x 100 μm Length: 180 cm (including 30 cm extension) Parallel rails Metalized holes for FPC connection Connectors?  Investigations ongoing with: CISEL (Castelfidardo, Italy) Industrial producer of Cu flat cables Interest to develop the technology for Al-based long flat cables Plating holes in-house or in outsourcing Plans: production of ~10 samples, estimated time 4 to 8 weeks (in house/outside) Laser cut: accuracy 100-200um PH-DT-DD (PCB workshop, contact: Rui de Oliveira) Design of test boards and PB dummy prototypes finalized Offer received today: 5um Al / 50um kapton+glue/ 25um Al Holes are not plated - No finishing and no solder mask Test board: 250 CHF - Long cable: 2900 CHF for 10 pieces (min) WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

10. 10  Semi-manual assembly procedure well advanced Handling and alignment: dies 50 μm thin and 15 x 30 mm 2 large Handling and alignment of FPC Shipping of HICs to the Stave construction centers under test Glued dummy HICs: Several samples already produced Chip position accuracy better than 5 μm Flatness quite good, to be verified with final components and soldering They are being used for the Stave assembly studies Soldered dummy HIC: Laser soldering of pre-glued single assemblies (back-up option) Laser soldering of a whole dummy HIC  end of May Dedicated jigs, compatible with the laser set-up, are being manufactured ITS objectives for 2014 – WP7 and WP8 4.Development of HIC assembly and test procedure and set-up (with WP4 and WP6) WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

11. 11 Semi-manual Assembly Procedure WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

12. Glued dummy HICs  Last batch: 10 samples without carbon plate for the studies of the Stave assembly 8 modules ready 2 modules to be completed by end of April 12WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

13. HICs shipping HIC box references holes for HIC box dummy HIC Pins for HIC pre-alignment Conductive carrying case for housing the 7-HICs shipping plate 1 2 345 6 7 HIC Alignment station foam 13WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

14.  Single chips soldered assemblies Chip on the back side Electrical daisy-chain test of 50 contacts Soldering of pre-glued single assemblies  2 pad chips glued to single-die FPCs 4 gluing dots glue: Eccobond 45 diameter: 600 µm thickness: 40 µm 14WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

15. Jigs for HIC soldering 1 3 2 4 Reference pins 15WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

16. 16 ITS objectives for 2014 – WP7 and WP8 5.Development of prototype of OB staves based on “pad chips”, dimensional survey and characterization (mechanical and thermal) (joint project with WP9)  Development of the Half-stave and Stave assembly procedure Alignment and gluing of HICs on the Coldplate ongoing Topic talk by Stefania  Milestones Coldplate equipped with dummy HICs and PB  July 2014 Following milestones Dummy Stave  beginning of 2015 Functional Half-stave  Spring 2015 WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

17. 17 ITS objectives for 2014 – WP7 and WP8 6.Development and characterization of HIC and Module (Stave?) based on Full-Scale Pixel Chips.  HIC-board prototype with 14 full-scale pixel chips to study system aspects Topic talk by Paul  Milestones HIC-board prototype with 14 full-scale pixel chips  July 2014 HIC prototype with Cu-FPC and 14 available full-scale pixel chips   December 2014 WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

18. 18 ITS objectives for 2014 – WP7 and WP8 7.Document on dimensional and position survey procedure (joint with WP6 and WP9)  Not yet started WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

19. Summary  Objectives for 2014 are on track  The study of few key system aspects should be started as soon as possible Power distribution Interconnections... 19WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014