1. Timer Interface Module MTT48 9 - 1 TIMER INTERFACE MODULE (TIM)

2. Timer Interface Module MTT48 9 - 2 Understand input capture function Understand output compare function Understand pulse width modulation functions Program TIM free running reference clock and options Configure any TIM channel as either: Input capture Output compare PWM Module Objectives Initialize TIM and timer reference counter for 250 ns resolution from 8 MHz system clock Configure channel 1 as input capture Configure channel 2 as output compare Configure channel 3 as buffered 75% duty cycle PWM TIM Module Exercises

3. Timer Interface Module MTT48 9 - 3 TIMER INTERFACE MODULE 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET Four programmable channels Input captures –Rising edge, falling edge, or any edge triggering Output compares –Set, clear, or toggle actions Pulse width modulation (PWM) –Buffered or Unbuffered signal generation Programmable clock input System clock with prescaler External TIM Clock input(4 MHz Maximum Frequency) Free-running or modulo up-count operation Counter overflow actions TIM Counter stop and reset DMA interrupt generation Modular Architecture Expandable to 8 Channels

4. Timer Interface Module MTT48 9 - 4 Timer Reference Block Diagram PRESCALER PRESCALER SELECT TCLK Internal BusClock PS2PS1PS0 INT Logic TSTOP PTE3/ TCLK 16-Bit Counter TRST 16-Bit ComparatorTMODH:TMODL TOF TOE To Channel Logic DataBusDataBus 16-Bit Latch

5. Timer Interface Module MTT48 9 - 5 Timer Clock Reference All four timer channels receive their clock reference from Free running counter Modulo up counter Consists of: 16 bit free running read only timer counter 16 bit software read/write modulo register 16 bit comparator (timer counter vs. modulo register) –When counter matches modulo register Timer Overflow Flag (TOF) set Counter resets to $0000 Counter begins counting again Generated from software selectable clock source External pin TCLK Output of 7 bit system clock prescaler

6. Timer Interface Module MTT48 9 - 6 Timer Status and Control Register (TSC) Clock select and prescaler bits (PS2-PS0) Timer Overflow Flag (TOF) Set when 16 bit timer counter resets to $0000 Cleared by reading TSC and then writing logic zero to TOF –If overflow occurs during clearing operation, write has no effect 1 = Timer has reset 0 = Timer has not reset yet Timer Overflow interrupt Enable (TOE) Enables timer overflow interrupt 1 = Enable interrupt 0 = Disable interrupt WRITE:0 TRST READ:TOF 00 RESET:00100000 TOETSTOP PS2 PS1PS0 TSC Timer Stop (TSTOP) –Stops the timer counter –Recommended1 = Timer stopped 0 = Timer active Timer Reset (TRST) –Resets timer counter AND prescaler –Automatically cleared after counter reset 1 = Reset counter and prescaler 0 = No effect NOTE: Setting both TSTOP and TRST stops the counter $0000

7. Timer Interface Module MTT48 9 - 7 PS2PS1PS0TIM Clock Source 000Internal Bus Clock ÷ 1 001Internal Bus Clock ÷ 2 010Internal Bus Clock ÷ 4 011Internal Bus Clock ÷ 8 100Internal Bus Clock ÷ 16 101Internal Bus Clock ÷ 32 110Internal Bus Clock ÷ 64 111PTE3/TCLK NOTE: TCLK pulses must be longer than two system clock pulses or will be ignored Timer Prescale Select Bits (PS0-2)

8. Timer Interface Module MTT48 9 - 8 Timer Counter Register Timer Counter Register (TCNTH, TCNTL) 16 bit, read only, free running counter Reading high byte latches low byte until read WRITE: READ:BIT 15BIT 14 BIT 13 BIT 12BIT 11 BIT 10 BIT 9 BIT 8 RESET:00000000 TCNTH WRITE: READ:BIT 7BIT 6 BIT 5 BIT 4BIT 3 BIT 2BIT 1BIT 0 RESET:00000000 TCNTL WRITE: READ: RESET:11111111 BIT 15BIT 14BIT 13 BIT 12BIT 11 BIT 10 BIT 9BIT 8 TMODH WRITE: READ: RESET:11111111 BIT 7 BIT 6BIT 5BIT 4 BIT 3 BIT 2 BIT 1BIT 0 TMODL Timer Modulo Register (TMODH, TMODL) Contents compare against TCNTH, TCHTL to determine reset time Writing to TMODH disables TOF and overflow interrupts, until write to TMODL Timer Modulo Register

9. Timer Interface Module MTT48 9 - 9 Timer Resolution and Range Timer resolution is inversely proportional to system clock and prescaler value Resolution (sec) = 1 ÷ (Bus Clock ÷ prescaler) Timer range depends on value in TMODH and TMODL Range = 0.. Resolution x TMOD value Max Range = 0.. Resolution x 65,535 Example: Calculate resolution and range given 4 MHz bus clock, prescaler value of 4 (010), and TMOD = $00FF Resolution = 1 ÷ ( 4 MHz ÷ 4 ) = 1 ÷ 1 MHz = 1µs Range = 1µs x $00FF = 1µs x 255 = 255 µs

10. Timer Interface Module MTT48 9 - 10 Timer Channel Block Diagram 16-bit Comparator CHANNEL X PTx Logic Int Logic CHxIE PTx/ TCHx MSxA TCHxH : TCHxL 16-bit Latch ELSxB X ELSxA CHxF DMASx TOVx CHxMAX From TOF DataBusDataBus

11. Timer Interface Module MTT48 9 - 11 Compare/Capture Unit 16-bit Free Running Counter 16-bit Input Capture Latch Status Flag is set upon capture Interrupt request to CPU08 LatchEdge Select & Detect ICx CHxF CHxIE Rising Edges Falling Edges Any Edge Optional Local Interrupt Mask (enabled through software) Provides a mechanism to capture the time at which an external event occurs TCNTH:TCNTHL TCHxH:TCHxL Input Capture Function

12. Timer Interface Module MTT48 9 - 12 Input Capture Example - Measured Pulse Width - T1 T2 1.Configure timer channel for input capture, rising edge 2.Capture time T1 3.Capture time T2 4.Period = T2 - T1

13. Timer Interface Module MTT48 9 - 13 Compare/Capture Unit 16-Bit Free-Running Counter 16-Bit Compare 16-Bit Output Compare Register (programmed by software) Pin Control Logic Interrupt request to CPU08 OCx CHxF Status Flag is set upon compare match CHxIE Optional Local Interrupt Mask (enabled through software) Provides a mechanism to output a signal at a specific time Set Pin Clear Pin Toggle Pin Action taken upon match of compare register with counter TCNTH:TCNTHL TCHxH:TCHxL Output Compare Function Possible uses: Generating waveforms or pulses Elapsed time indicator (to external circuitry) Triggering external events

14. Timer Interface Module MTT48 9 - 14 Output Compare Example - Pulse Generation - 1.Set compare value to T1 2. Configure timer channel for output compare, set output 3.Set compare value to T2 4.Configure timer channel for output compare, clear output 5.Generated pulse width = T2 - T1 T1 T2

15. Timer Interface Module MTT48 9 - 15 Interrupt latency and execution time may limit minimum pulse width possible using interrupt on overflow method To maximize resolution and avoid unsynchronized writes: Enable the output compare interrupt function when new pulse width value required Write new value to output compare register within output compare interrupt routine Output Compare Synchronization Method

16. Timer Interface Module MTT48 9 - 16 Timer Overflow Action Timer Channel Status and Control Registers (TSCx) Toggle on Overflow (TOVx) –Controls behavior Output Compare and PWM only –Has no effect when channel configured as input capture –Normal used in generating PWMs 1 = Toggle Channel output on Timer Overflow 0 = Do nothing on Timer Overflow WRITE: 0 READ:CHxF RESET:00000000 x = Channel number 0, 1, 2, etc. CHxIE MSxBMSxAELSxB ELSxA TOVx CHxMAX TSCx

17. Timer Interface Module MTT48 9 - 17 Channel Timer Registers Timer Channel registers (TCHx) Input Capture –Timer register value latched upon input capture Output Compare –Value to compare timer against WRITE: READ: RESET:INDETERMINATE AFTER RESET BIT 15BIT 14BIT 13 BIT 12BIT 11 BIT 10 BIT 9BIT 8 TCHxH WRITE: READ: RESET:INDETERMINATE AFTER RESET x = Channel number 0, 1, 2, etc. BIT 7 BIT 6BIT 5BIT 4 BIT 3 BIT 2 BIT 1BIT 0 TCHxL

18. Timer Interface Module MTT48 9 - 18 Mode, Edge, and Level Selection X000Output PresetPin under port control; initial output lvl high X100Output PresetPin under port control; initial output lvl low 0001Input CaptureCapture on Rising Edge Only 0010Input CaptureCapture on Falling Edge Only 0011Input CaptureCapture on ANY (rising or falling) Edge 0101Output CompareToggle output line on Output Compare 0110 OrClear output line to 0 on output compare 0111 PWMSet output line to 1 on output compare 1X01Buffered OutputToggle output on compare 1X10Compare OrClear output on compare 1X10Buffered PWMSet output on compare MSxB:MSxAELSxB:ELSxA Mode Configuration Note 1: MSxB has priority over MSxA (When MSxB is set, MSxA is don't care) Note 2: Unbuffered PWMs are set up while in Output Compare Mode WRITE: 0 READ:CHxF RESET:00000000 x = Channel number 0, 1, 2, etc. CHxIE MSxBMSxAELSxB ELSxA TOVx CHxMAX TSCx

19. Timer Interface Module MTT48 9 - 19 Channel Interrupt & Status Timer Channel Status and Control Registers (TSCx) Channel x Interrupt Enable (CHxE) – Enables TIM CPU interrupts and TIM DMA service requests on channel x. 1 = Channel x CPU interrupt requests and DMA service requests enabled 0 = Channel x CPU interrupt requests and DMA service requests disabled Channel Status Flag (CHxF) – Input Capture Set when active edge occurs –Output Compare Set when the value in TIM counter registers matches value in TIM channel register –Cleared by reading status register then writing logic one to CHxF 1 = Input capture or output compare on channel x 0 = No event capture or output compare on channel x WRITE: 0 READ:CHxF RESET:00000000 x = Channel number 0, 1, 2, etc. CHxIE MSxBMSxAELSxB ELSxA TOVx CHxMAX TSCx

20. Timer Interface Module MTT48 9 - 20 TIM Exercise Calculate the register values to configure: Timer for 8µs resolution from a 4 MHz Bus clock Timer channel 1 to capture rising edge of a signal Timer channel 2 to toggle it’s output between states every 100 ms Given: MCU has just been reset * Timer exercise TSCEQU$0020 TMODHEQU$0024 TMODLEQU$0025 TSC1EQU$0029 TSC2EQU$002C TCH2HEQU$002D TCH2LEQU$002E * Configure Timer for 8µs resolution, using 4 MHz system clock MOV#_30_,TSC; Reset timer, Configure clock prescaler MOV#_30_,TMODH;MSB for modulo register MOV#_D4_,TMODL;LSB for modulo register * Configure Timer channel 1 to capture rising edge of pulse MOV#_04_,TSC1;Input capture, rising edge only, no interrupts * Configure Timer channel 2 to toggle output MOV#_30_,TCH2H;Set compare value MSB MOV#_D4_,TCH2L;Set compare value LSB MOV#_14_,TSC2;Output compare, toggle output, no interrupts BCLR5,TSC;Start timer, reset bit automatically clear

21. Timer Interface Module MTT48 9 - 21 Measure Period of a Square Wave Exercise Write a routine that measures the period of a square wave on TCH1. The routine uses the Input Capture function to determine the difference in time from one rising edge to the next. Use a software polling, non-interrupt-driven, routine. Assume System clock = 8 MHz. Suggested program steps: Address of Time (16 bit value) Address of Difference (16 bit value) Addresses for: Timer Status/Control Register Timer Ch. 1 Status/Control Register Timer Ch. 1 High Register Timer Ch. 1 Low Register Timer Counter Register High Timer Counter Register Low Write your program here: TIME EQU $50 DIFF EQU $52 TSC EQU $20 TSC1 EQU $29 TCH1H EQU $2A TCH1L EQU $2B TCNTH EQU $22 TCNTL EQU $23 Get time of next rising edge of square wave & calculate difference between first and next times: 10. Wait here if CH1F flag is not set, else goto 11. 11. Load TCH1L count into accumulator. 12. Subtract TIMEL from accumulator. 13. Store difference to DIFFL RAM location. 14. Load TCH1H count into accumulator. 15. Subtract with borrow TIMEH from accumulator. 16. Store difference to DIFFH RAM location. 17. Done, stay here. HC08-InCapExer Configure Timer for 8uS resolution, using 8MHz clock 1. Reset Timer and Configure clock Prescaler Initialize TIM CH1 for input capture function: 2. Load TCR with "capture rising edge" value. Clear TIM CH1 flag (CH1F), Start Timer; 3. Read Timer Channel 1 Status Register. 4. Write a logic "zero" to CH1F. 5. Start timer, reset bit automatically clears. Get time of first rising edge of square wave & clear CH1F: 6. Wait here if CH1F flag is not set, else goto 7. Also, first step to clear CH1F flag 7. Load TCH1H count into H:X Register. 8. Store H:X to TIME RAM location. 9. Second step to clear CH1F flag(Write "0" to CH1F)

22. Timer Interface Module MTT48 9 - 22 Suggested program steps: Addresses for: Timer Status/Control Register Timer Ch. 2 Status/Control Register Timer Ch. 2 High Register Timer Ch. 2 Low Register Timer Counter Register High Timer Counter Register Low 1 KHz Square Wave Exercise Write a routine that generates a 1 KHz square wave on the TCH2 pin. Assume the internal processor clock = 4 MHz. Use a software polling, non-interrupt driven, routine. D = Delay from one TCMP clock edge to the next = 500 uSec F (timer clock Frequency) = 4 MHz ÷ 4 = 1 MHz Total # of timer clocks = F x D = (1 x 10 E6) x (500 x 10 E-6) = 500 13. Add with carry TCH2H to accumulator. 14. Store accumulator to TCH2H. 15. Get saved delay for TCH2L. 16. Store accumulator to TCH2L. 17. Write a logic "0" to CH2F, 2nd step to clear flag. 18. Goto step 8. HC08-OutCompExer Write your program here: TSC EQU $20 TSC2 EQU $2C TCH2H EQU $2D TCH2L EQU $2E TCNTH EQU $22 TCNTL EQU $23 Configure Timer for 8uS resolution, using 8MHz clock 1. Reset Timer and Configure clock Prescaler Initialize TIM CH2 to toggle output every 1mS 2. Set MSB compare value. 3. Set LSB compare value. 4. Load TSC2 with "Toggle output on compare" value. Clear CH2F flag(2 steps required): 5. Read TSC2. 6. Write a logic "0" to CH2F. 7. Start Timer When CH2F=1 add 500 usec. delay & set for next output: 8. Wait for CH2F to go set, also 1st. step to clear flag 9. Load Accumulator with low half of 500 usec delay. 10. Add TCH2L value to accumulator. 11. Save accumulator. 12. Load accumulator with hi half of 500 usec delay.

23. Timer Interface Module MTT48 9 - 23 Unbuffered PWM Signal Any channel can generate an unbuffered PWM Uses output compare Toggling output based on timer overflow PWM period set by: Modulo count value Clock prescaler output Pulse width duration set by: Output compare register value –Timer channel configured to force output pin to complement of pulse width level

24. Timer Interface Module MTT48 9 - 24 PWM Signal Generation T1 = PWM Period = Timer overflow point Calculate prescaler value and TMOD = T1 T2 = Pulse width = Output compare value Example: Want 50% duty cycle PWM with period of 100 µs from a 4 MHz system clock. Select prescaler of 4, Resolution = 1 ÷ (4 MHz ÷ 4) = 1µs TMOD = T1 ÷ Resolution = 100µs ÷ 1µs = 100 TCHxH:TCHxL = T2 = Duty cycle x TMOD = 50% x 100 = 50 A = Output compare, clear output occursB = Timer overflow, toggle output occurs T2 T1 A BA B A TIME

25. Timer Interface Module MTT48 9 - 25 PWM Resolution Period 8-bit PWMs –Variable in 256 increments of system clock 16-bit PWMs –Variable in 65536 increments of system clock Pulse width is variable up to N increments of system clock N = System clock counts for Period –Pulse width = N/4 = 25% duty cycle –Pulse width = N/2 = 50% duty cycle –Pulse width = 3N/4 = 75% duty cycle

26. Timer Interface Module MTT48 9 - 26 Unbuffered PWM Initialization 1)Stop and reset timer 2)Select timer counter modulo value and timer clock prescaler to provide required PWM period 3)Load output compare register with pulse width value 4)Configure timer channel for output compare operation 5)Select the timer counter toggle on overflow function 6)Configure timer channel to force output pin to complement of pulse width level Toggle on output compare should not be used 7)Enable the timer

27. Timer Interface Module MTT48 9 - 27 Create an eight-bit unbuffered PWM with the following characteristics: Frequency of approx 32 KHz Duty cycle of 75% Initial Pulse Width begins in logic 1 state Assume: 8 MHz system clock Use timer channel 0 HC08 has just been reset Steps Required: Stop and reset timer Set TSTOP and TRST in TSC register Configure prescaler and modulo register for 32 KHz Note PS2:0 in TSC register = 000 (divide by 1) on timer reset Set TMODH:TMODL = $00FF (8 MHz / 256 ­ 32 KHz) Configure timer status and control register for channel 0 (TSC0) Set MS0A = 1 (Output Compare) Set ELS0B:ELS0A = 10 (Clear output line on output compare) Set TOV0 = 1 (Enable timer counter toggle on overflow) Clear CH0E (Disable output compare interrupt) Load output compare register for pulse width of 192 counts Set TCH0H = $00, TCH0L = $C0 (192 / 256 = 75%) Enable the timer Clear TSTOP in the TSC register Unbuffered PWM “Example 1” Frequency ~ 32Khz (8Mhz/256) Pulse Width Duration= 75% Duty Cycle 192 256

28. Timer Interface Module MTT48 9 - 28 Limitation for Unbuffered PWM Previous methods for changing pulse widths work in most cases Except when change in pulse width is large Example: Could not change from a 99% duty cycle to a 1% duty cycle

29. Timer Interface Module MTT48 9 - 29 Buffered PWM Channel Block Diagram

30. Timer Interface Module MTT48 9 - 30 What is Buffered PWM? Uses two output compare registers to control a single output Overcomes synchronization and pulse width limitations of unbuffered PWMs Channels 0 and 1 and/or channels 2 and 3 may be linked Selected by setting MS0B and/or MS2B bit Linked timer channel (ch 1 and/or 3) output becomes general purpose I/O –Under control of DDR and data register –Regardless of TSC1 and/or TSC3 settings HC08 Buffered PWM Operation Configure either channel 0 or 2 as for unbuffered PWM Except MSxB bit is set in TSCx register Initial pulse width must be loaded into channel 0 or 2’s output compare register Subsequent pulse width values are written to inactive linked channel at any time Writing to compare register of inactive channel enables that channel Output control changes after next counter overflow –Auto synchronization

31. Timer Interface Module MTT48 9 - 31 Buffered PWM “ Example 1 “ Create an eight-bit buffered PWM with following characteristics: Frequency of approximately Assume: System clock is approx 8 Mhz Use timer channels 0 and 1 HC08 has just been reset Frequency ~ 32Khz (8Mhz/256) Pulse Width Duration = 254 counts

32. Timer Interface Module MTT48 9 - 32 Stop and reset the timer Set TSTOP and TRST in TSC register Configure prescaler and TMOD register for 32 KHz Note PS2:0 in TSC register = 000 (divide by 1) on timer reset Set TMODH:TMODL = $00FF (8 MHz / 256 ­ 32 KHz) Configure timer status and control register for channel 0 (TSC0) Set MS0B:MS0A = 11 (Buffered PWM, Output Compare) Set ELS0B:ELS0A = 10 (Clear output line on output compare) Set TOV0 = 1 (Enable timer counter toggle on overflow) Clear CH0E (Disable output compare interrupt) Load output compare register 0 for pulse width of 254 counts Set TCH0H = $00, TCH0L = $FE (254 / 256 = 99%) Enable the timer Clear TSTOP in TSC register Buffered PWM “ Example 1 Solution “ Frequency = 32Khz Pulse Width = 254

33. Timer Interface Module MTT48 9 - 33 Pulse Width Modulation Buffered/Unbuffered Unbuffered PWMs Advantages –Consistent, non-serviced PWM waveform –Programmable period and duty cycle Disadvantage –Must synchronize changes to duty cycle Buffered PWMs Advantages –Unsynchronized changes to duty cycle, auto sync Disadvantage –Requires two timer channels –Must keep track of inactive channel

34. Timer Interface Module MTT48 9 - 34 TIM Exercise - Buffered PWM - Code configures a Timer channel as a buffered 75% duty cycle PWM. Assume: Timer register already configured for 125 ns resolution TMOD register has not been initialized (default $FFFF) Pick your own PWM frequency/period Given: * Timer exercise - Part 2 TSCEQU$0020 TMODHEQU$0024 TMODLEQU$0025 TSC0EQU$0026 TCH0HEQU$0027 TCH0LEQU$0028 TSC1EQU$0029 TCH1HEQU$002A TCH1LEQU$002B * Timer exercise - Part 2 BSET5,TSC;Stop timer BSET 4,TSC;Reset timer * Could pick any period you want, lets choose max in 8-bit PWM, yields ­ 32 KHz MOV#$00,TMODH;MSB for modulo register MOV#$FF,TMODL;LSB for modulo register *Want 75% duty cycle = 3/4 * period = 3/4 * 256 = 192 MOV#$00,TCH0H;Set compare value MSB MOV#$C0,TCH0L;Set compare value LSB * Configure Timer channel 0 as buffered PWM MOV#$2A,TSC0;Buffered PWM, Clear on compare, Enable ;toggle on timer overflow BCLR5,TSC;Start timer, reset bit automatically clear

35. Timer Interface Module MTT48 9 - 35 Additional Timer Questions a)What is the fastest frequency that can be achieved for a 5-bit PWM? b)What is the fastest frequency that can be achieved for a 12-bit PWM? c)What happens when an output compare value is greater than the value in the modulus registers? d)What happens if the output compare register is the same as the modulus register e)With ELSxB:ELSxA = 00 (discrete I/O mode), will the timer still generate interrupts if enabled? f)How do you force an output compare or PWM to begin in a logic zero or logic one state?

36. Timer Interface Module MTT48 9 - 36 Additional Timer Questions ANSWERS a)Bus Clock/32 ~ 8Mhz/32 ~ 250 KHz b)Bus Clock/4096 ~ 8Mhz/4096 ~ 2 KHz c)The output compare will never occur if the Output Compare register is greater than the modulus register d)The counter overflow toggle will take precedence (if enabled) over an output compare if they occur at the same time e)Yes. You must disable the channel interrupts or stop the timer to disable timer interrupts

37. Timer Interface Module MTT48 9 - 37 f)To force a channel output to a logic zero: Set ELSxB:ELSxA = 10 Ensure (MSxB:)MSxA are set to any state other than (0)0 Clear the appropriateReset the timer (TRST = 1) To force a channel output to a logic one: Set ELSxB:ELSxA = 11 Ensure (MSxB:)MSxA are set to any state other than (0)0 Clear the appropriateReset the timer (TRST = 1) Note: You cannot use I/O port data register and DDR to preset state of an output pin prior to enabling timer channel Additional Timer Questions ANSWERS

38. Timer Interface Module MTT48 9 - 38 100% Duty Cycle Selection Timer Channel Status and Control Registers (TSC0 - TSC3) Channel Max - 100% PWM duty cycle (CHxMAX) –Forces duty cycle to 100% –Takes effect in cycle after being set or cleared 1 = Enable 100 % duty cycle 0 = Disabled WRITE: 0 READ:CHxF RESET:00000000 x = Channel number 0, 1, 2, etc. CHxE MSxB MSxAELSxB ELSxA TOVx CHxMAX TSCx

39. Timer Interface Module MTT48 9 - 39 Additional Information - DMA Servicing - Timer DMA Select Register (TDMA) DMA Channel Selects ( DMAS3 - DMAS0) –Selects either CPU or DMA interrupts for that channel 1 = DMA handles channel x interrupts 0 = CPU handles channel x interrupts NOTE: Channel interrupts are still enabled/disabled by CHxE bit in TSCx register WRITE: READ:0 000 RESET:00000000 DMA3S DMA2S DMA1SDMA0S TDMA

40. Timer Interface Module MTT48 9 - 40 Additional Information - Low Power Modes - WAIT TIM remains active TIM Registers are not accessible by the CPU Enabled TIM interrupts can wake processor DMA can service the TIM without exiting wait mode If TIM functions are not required during wait mode, stop TIM before executing WAIT instruction STOP TIM becomes inactive Register contents not affected TIM operation resumes when the MCU exits stop mode after and external interrupt

41. Timer Interface Module MTT48 9 - 41 Register Summary TSC TOFTOIETSTOPTRST0PS2PS1PS0 TDMA 0000DMAS3DMAS2DMAS1DMAS0 TCNTH BIT 15BIT 14BIT 13BIT 12BIT 11BIT 10BIT 9BIT 8 TCNTL BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 TMODH BIT 15BIT 14BIT 13BIT 12BIT 11BIT 10BIT 9BIT 8 TMODL BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 TCS0 CH0FCH0IEMS0BMS0AELS0BELS0ATOV0 CH0MX TCH0H BIT 15BIT 14BIT 13BIT 12BIT 11BIT 10BIT 9BIT 8 TCH0L BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 TCSn CHnFCHnIE0MSnAELSnBELSnATOVn CHnMX TCHnH BIT 15BIT 14BIT 13BIT 12BIT 11BIT 10BIT 9BIT 8 TCHnL BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

42. Timer Interface Module MTT48 9 - 42

43. Timer Interface Module MTT48 9 - 43 Suggested program steps: Addresses for: Timer Status/Control Register Timer Ch. 2 Status/Control Register Timer Ch. 2 High Register Timer Ch. 2 Low Register Timer Counter Register High Timer Counter Register Low 1 KHz Square Wave Exercise Write a routine that generates a 1 KHz square wave on the TCH2 pin. Assume the internal processor clock = 4 MHz. Use a software polling, non-interrupt driven, routine. D = Delay from one TCMP clock edge to the next = 500 uSec F (timer clock Frequency) = 4 MHz ÷ 4 = 1 MHz Total # of timer clocks = F x D = (1 x 10 E6) x (500 x 10 E-6) = 500 13. Add with carry TCH2H to accumulator. 14. Store accumulator to TCH2H. 15. Get saved delay for TCH2L. 16. Store accumulator to TCH2L. 17. Write a logic "0" to CH2F, 2nd step to clear flag. 18. Goto step 8. HC08-OutCompSol Write your program here: TSC EQU $20 TSC2 EQU $2C TCH2H EQU $2D TCH2L EQU $2E TCNTH EQU $22 TCNTL EQU $23 Configure Timer for 8uS resolution, using 8MHz clock 1. Reset Timer and Configure clock Prescaler Initialize TIM CH2 to toggle output every 1mS 2. Set MSB compare value. 3. Set LSB compare value. 4. Load TSC2 with "Toggle output on compare" value. Clear CH2F flag(2 steps required): 5. Read TSC2. 6. Write a logic "0" to CH2F. 7. Start Timer When CH2F=1 add 500 usec. delay & set for next output: 8. Wait for CH2F to go set, also 1st. step to clear flag 9. Load Accumulator with low half of 500 usec delay. 10. Add TCH2L value to accumulator. 11. Save accumulator. 12. Load accumulator with hi half of 500 usec delay. MOV #$36,TSC MOV #$F4,TCH2H MOV #$01,TCH2L MOV #$14,TSC2 BCLR #7,TSC2 BCLR #5,TSC WAIT BRCLR #7,TSC2,WAIT LDA #$F4 ADD TCH2L TAX LDA #1 ADC TCH2H STA TCH2H STX TCH2L BCLR #7,TSC2 BRA WAIT

44. Timer Interface Module MTT48 9 - 44 Timer Block Diagram PRESCALER PRESCALER SELECT TCLK INTERNAL 16-BIT COMPARATOR PS2PS1PS0 16-BIT COMPARATOR 16-BIT LATCH TCH0H:TCH0L MS0A ELS0BELS0A PTE4 TOF TOIE INTER- 16-BIT COMPARATOR 16-BIT LATCH TCH1H:TCH1L 16-BIT COMPARATOR 16-BIT LATCH TCH2H:TCH2L 16-BIT COMPARATOR 16-BIT LATCH TCH3H:TCH3L CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 TMODH:TMODL TRST TSTOP TOV0 CH0IE DMA0S CH0F ELS1BELS1A TOV1 CH1IE DMA1S CH1MAX CH1F ELS2BELS2A TOV2 CH2IE DMA2S CH2MAX CH2F ELS3BELS3A TOV3 CH3IE DMA3S CH3MAX CH3F CH0MAX MS0B MS2B 16-BIT COUNTER BUS CLOCK MS1A MS2A MS3A PTE3/TCLK PTE4/TCH0 PTE5/TCH1 PTE6/TCH2 LOGIC RUPT LOGIC INTER- RUPT LOGIC PTE5 LOGIC INTER- RUPT LOGIC PTE6 LOGIC INTER- RUPT LOGIC PTE7 LOGIC INTER- RUPT LOGIC PTE7/TCH3 INTERNAL BUS TIM V2.1 9 - 12