1. Verilog for Digital Design
Chapter 3:
Sequential Logic Design

2. Must know sequence of past inputs to know output
3.1
Introduction
Sequential circuit
Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs
Stores bits, also known as having “state”
Simple example: a circuit that counts up in binary
In this chapter, we will:
Design a new building block, a flip-flop, that stores one bit
Combine that block to build multi-bit storage – a register
Describe the sequential behavior using a finite state machine
Convert a finite state machine to a controller – a sequential circuit having a register and combinational logic 1 a 1
Combinational
digital circuit F b 1 a ?
Sequential
digital circuit F b si
ansis
Must know sequence of past inputs to know output e z
Note: Slides with animation are denoted with a small red "a" near the animated items

3. Example Needing Bit Storage
3.2
Example Needing Bit Storage
Bit
Storage
Blue light
Call
button
Cancel
Flight attendant call button
Press call: light turns on
Stays on after button released
Press cancel: light turns off
Logic gate circuit to implement this?
1. Call button pressed – light turns on
Bit
Storage
Blue light
Call
button
Cancel
2. Call button released – light stays on a Q
Call
Cancel
Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0
Need some form of “feedback” in the circuit
Bit
Storage
Blue light
Call
button
Cancel
3. Cancel button pressed – light turns off a

4. Clocks Clock period: time interval between pulses
Above signal: period = 20 ns
Clock cycle: one such time interval
Above signal shows 3.5 clock cycles
Clock frequency: 1/period
Above signal: frequency = 1 / 20 ns = 50 MHz
1 Hz = 1/s
100 GHz
10 GHz
1 GHz
100 MHz
10 MHz
0.01 ns
0.1 ns
1 ns
10 ns
100 ns
Period
Freq

5. Note: Hundreds of different flip-flop designs exist
D Flip-Flop
Flip-flop: Bit storage that stores on clock edge, not level
One design -- master-servant
Two latches, output of first goes to input of second, master latch has inverted clock signal
So master loaded when C=0, then servant when C=1
When C changes from 0 to 1, master disabled, servant loaded with value that was at D just before C changed -- i.e., value at D during rising edge of C
Clk
rising edges
Note: Hundreds of different flip-flop designs exist
D latch
master
servant D Dm Ds Cs Qm Q s ’ Qs C m
Clk
D flip-flop

6. D Flip-Flop Q ’ D D Q ’ Q Symbol for rising-edge triggered D flip-flop
Internal design: Just invert servant clock rather than master
The triangle means clock input, edge triggered Q
Symbol for rising-edge
triggered D flip-flop
Symbol for falling-edge
triggered D flip-flop
Clk
rising edges
falling edges
Clk

7. Two latches inside each flip-flop
D Flip-Flop
Solves problem of not knowing through how many latches a signal travels when C=1
In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B
Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously -- then all four no longer pay attention to their input, until the next rising edge. Doesn’t matter how long Clk is 1. D1 Q1 D2 Q2 D3 Q3 D4 Q4 Y
Clk
Clk_A
Clk_B T w
o l a t
fli
Two latches inside each flip-flop

8. Flight-Attendant Call Button Using D Flip-Flop
D flip-flop will store bit
Inputs are Call, Cancel, and present value of D flip-flop, Q
Truth table shown below C
all
but t on an c el
Flight
attendant
call-button
system
Blue
light
Preserve value: if Q=0, make D=0; if Q=1, make D=1
Circuit derived from truth table, using Chapter 2 combinational logic design process
Cancel -- make D=0 D Q’ Q
Clk C
all
but t on an c el
Blue
light
Call
Cancel
Call -- make D=1 Q
Let’s give priority to Call -- make D=1

9. Basic Register Typically, we store multi-bit items
e.g., storing a 4-bit binary number
Register: multiple flip-flops sharing clock signal
From this point, we’ll use registers for bit storage
No need to think of latches or flip-flops
But now you know what’s inside a register

10. Example Using Registers: Temperature Display
Temperature history display
Sensor outputs temperature as 5-bit binary number
Timer pulses C every hour
Record temperature on each pulse, display last three recorded values a4 x4 x3 x2 x1 x0 C a3 a2 a1 a0 t
empe r a tu e
sensor
timer
Display
Present b4 b3 b2 b1 b0
TemperatureHistoryStorage
1 hour ago c4 c3 c2 c1 c0
2 hours ago
(In practice, we would actually avoid connecting the timer output
C to a clock input, instead only connecting an oscillator output to a clock input.)

11. Example Using Registers: Temperature Display
Use three 5-bit registers Q4 C x4 x3 x2 x1 x0 Q3 Q2 Q1 Q0 R a b I 4 3 2 1 a4 a3 a2 a1 a0 c b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
TemperatureHistoryStorage 15 18 20 21 24 25 26 27 22
x4...x0 C R a b c

12. D Latch vs. D Flip-Flop Latch is level-sensitive: Stores D when C=1
Flip-flop is edge triggered: Stores D when C changes from 0 to 1
Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is redundant
Two types of flip-flops -- rising or falling edge triggered.
Comparing behavior of latch and flip-flop:

13. Register Behavior

14. Register Behavior Sequential circuits have storage
Register: most common storage component
N-bit register stores N bits
Structure may consist of connected flip-flops I 3 I 2 I 1 I
reg(4)
Rst Q3 Q2 Q1 Q0 I 3 I 2 I 1 I
4-bit register D D D D Q Q Q Q
Clk R R R R
Rst Q3 Q2 Q1 Q0

15. Register Behavior Vectors
Typically just describe register behaviorally
Declare output Q as reg variable to achieve storage
Uses vector types
Collection of bits
More convenient than declaring separate bits like I3, I2, I1, I0
Vector's bits are numbered
Options: [0:3], [1:4], etc.
[3:0]
Most-significant bit is on left
Assign with binary constant (more on next slide) I 3 I 2 I 1 I
reg(4)
Rst Q3 Q2 Q1 Q0
`timescale 1 ns/1 ns
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
input Clk, Rst;
Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule
module Reg4(I3,I2,I1,I0,Q3,...);
input I3, I2, I1, I0; I3 I2 I1 I0
module Reg4(I, Q, ...);
input [3:0] I; I:
I[3]
I[2]
I[1]
I[0]
vldd_ch3_Reg4.v

16. Register Behavior Constants
Binary constant
4'b0000
4: size, in number of bits
'b: binary base
0000: binary value
Other constant bases possible
d: decimal base, o: octal base, h: hexadecimal base
12'hFA2
'h: hexadecimal base
12: 3 hex digits require 12 bits
FA2: hex value
Size is always in bits, and optional
'hFA2 is OK
For decimal constant, size and 'd optional
8'd255 or just 255
In previous uses like “A <= 1;” 1 and 0 are actually decimal numbers. ‘b1 and ‘b0 would explicitly represent bits
Underscores may be inserted into value for readability
12'b1111_1010_0010
8_000_000 I 3 I 2 I 1 I
reg(4)
Rst Q3 Q2 Q1 Q0
`timescale 1 ns/1 ns
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
input Clk, Rst;
Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule
vldd_ch3_Reg4.v

17. Register Behavior Procedure's event control involves Clk input
Not the I input. Thus, synchronous
"posedge Clk"
Event is not just any change on Clk, but specifically change from 0 to 1 (positive edge)
negedge also possible
Process has synchronous reset
Resets output Q only on rising edge of Clk
Process writes output Q
Q declared as reg variable, thus stores value too I 3 I 2 I 1 I
reg(4)
Rst Q3 Q2 Q1 Q0
`timescale 1 ns/1 ns
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
input Clk, Rst;
Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule
vldd_ch3_Reg4.v

18. Register Behavior Testbench
`timescale 1 ns/1 ns
module Testbench();
reg [3:0] I_s;
reg Clk_s, Rst_s;
wire [3:0] Q_s;
Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s);
// Clock Procedure
always begin
Clk_s <= 0;
#10;
Clk_s <= 1;
end // Note: Procedure repeats
// Vector Procedure
initial begin
Rst_s <= 1;
I_s <= 4'b0000;
@(posedge Clk_s);
#5 Rst_s <= 0;
I_s <= 4'b1010;
I_s <= 4'b1111;
end
endmodule
Register Behavior Testbench
reg/wire declarations and module instantiation similar to previous testbenches
Module uses two procedures
One generates 20 ns clock
0 for 10 ns, 1 for 10 ns
Note: always procedure repeats
Other provides values for inputs Rst and I (i.e., vectors)
initial procedure executes just once, does not repeat
(more on next slide)
vldd_ch3_Reg4TB.v

19. Register Behavior Testbench
`timescale 1 ns/1 ns
module Testbench();
reg [3:0] I_s;
reg Clk_s, Rst_s;
wire [3:0] Q_s;
Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s);
// Clock Procedure
always begin
Clk_s <= 0;
#10;
Clk_s <= 1;
end // Note: Procedure repeats
// Vector Procedure
initial begin
Rst_s <= 1;
I_s <= 4'b0000;
@(posedge Clk_s);
#5 Rst_s <= 0;
I_s <= 4'b1010;
I_s <= 4'b1111;
end
endmodule
Register Behavior Testbench
Variables/nets can be shared between procedures
Only one procedure should write to variable
Variable can be read by many procedures
Clock procedure writes to Clk_s
Vector procedures reads Clk_s
Event control Clk_s)"
May be prepended to statement to synchronize execution with event occurrence
Statement may be just ";" as in example
In previous examples, the “statement” was a sequential block (begin-end)
Test vectors thus don't include the clock's period hard coded
Care taken to change input values away from clock edges
vldd_ch3_Reg4TB.v

20. Register Behavior Testbench
...
// Vector Procedure
initial begin
Rst_s <= 1;
I_s <= 4'b0000;
@(posedge Clk_s);
#5 Rst_s <= 0;
I_s <= 4'b1010;
I_s <= 4'b1111;
end
Simulation results
Note that Q_s updated only on rising clock edges
Note Q_s thus unknown until first clock edge
Q_s is reset to “0000” on first clock edge
vldd_ch3_Reg4TB.v
I_s
Q_s
time (ns) 10 20 30 40
Clk_s 50 70
0000
1010
1111
xxxx
Rst_s 60 80
...
Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
Remember that Q_s is connected to Q, and I_s to I, in the testbench
vldd_ch3_Reg4.v
Initial value of a bit is the unknown value x

21. Common Pitfalls Using "always" instead of "initial" procedure
// Vector Procedure
always begin
Rst_s <= 1;
I_s <= 4'b0000;
@(posedge Clk_s);
...
#5 Rst_s <= 0;
I_s <= 4'b1111;
end
Using "always" instead of "initial" procedure
Causes repeated procedure execution
Not including any delay control or event control in an always procedure
May cause infinite loop in the simulator
Simulator executes those statements over and over, never executing statements of another procedure
Simulation time can never advance
Symptom – Simulator appears to just hang, generating no waveforms
// Vector Procedure
always begin
Rst_s <= 1;
I_s <= 4'b0000;
end
time (ns)
I_s
Q_s 10 20 30 40
Clk_s 50 70
Rst_s 60 80

22. Common Pitfalls Not initializing all module inputs
May cause undefined outputs
Or simulator may initialize to default value. Switching simulators may cause design to fail.
Tip: Immediately initialize all module inputs when first writing procedure
// Vector Procedure
always begin
Rst_s <= 1;
I_s <= 4'b0000;
@(posedge Clk_s);
...
#5 Rst_s <= 0;
I_s <= 4'b1111;
end

23. Common Pitfalls
Forgetting to explicitly declare as a wire an indentifier used in a port connection
e.g., Q_s
Verilog implicitly declares identifier as a net of the default net type, typically a one-bit wire
Intended as shortcut to save typing for large circuits
May not give warning message during compilation
Works fine if a one-bit wire was desired
But may be mismatch – in this example, the wire should have been four bits, not one bit
Unexpected simulation results
Always explicitly declare wires
Best to avoid use of Verilog's implicit declaration shortcut
`timescale 1 ns/1 ns
module Testbench();
reg [3:0] I_s;
reg Clk_s, Rst_s;
wire [3:0] Q_s;
Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s);
...

24. Finite-State Machines (FSMs)—Sequential Behavior

25. Finite-State Machines (FSMs) and Controllers
3.3
Finite-State Machines (FSMs) and Controllers
Want sequential circuit with particular behavior over time
Example: Laser timer
Push button: x=1 for 3 clock cycles
How? Let’s try three flip-flops
b=1 gets stored in first D flip-flop
Then 2nd flip-flop on next cycle, then 3rd flip-flop on next
OR the three flip-flop outputs, so x should be 1 for three cycles
Controller x b
clk
laser
patient

26. Need a Better Way to Design Sequential Circuits
Trial and error is not a good design method
Will we be able to “guess” a circuit that works for other desired behavior?
How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10 cycles? Detecting the sequence in binary on a 3-bit input?
And, a circuit built by guessing may have undesired behavior
Laser timer: What if press button again while x=1? x then stays one another 3 cycles. Is that what we want?
Combinational circuit design process had two important things
A formal way to describe desired circuit behavior
Boolean equation, or truth table
A well-defined process to convert that behavior to a circuit
We need those things for sequence circuit design

27. Describing Behavior of Sequential Circuit: FSM
Finite-State Machine (FSM)
A way to describe desired behavior of sequential circuit
Akin to Boolean equations for combinational behavior
List states, and transitions among states
Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle
Two states: “Off” (x=0), and “On” (x=1)
Transition from Off to On, or On to Off, on rising clock edge
Arrow with no starting state points to initial state (when circuit first starts)
Outputs: x On O ff
x=0
x=1
clk ^

28. FSM Example: 0,1,1,1,repeat Want 0, 1, 1, 1, 0, 1, 1, 1, ...
Each value for one clock cycle
Can describe as FSM
Four states
Transition on rising clock edge to next state
Outputs: x
On1 O ff
On2
On3
clk ^
x=1
x=0 O ff
On1
On2
On3
clk x
State
Outputs:

29. Extend FSM to Three-Cycles High Laser Timer
On2
On1
On3 O ff
clk ^
x=1
x=0 b
’*clk
b*clk
Inputs: b; Outputs: x
Four states
Wait in “Off” state while b is 0 (b’)
When b is 1 (and rising clock edge), transition to On1
Sets x=1
On next two clock edges, transition to On2, then On3, which also set x=1
So x=1 for three cycles after button pressed

30. FSM Simplification: Rising Clock Edges Implicitff
x=1
x=0 b’
clk ^
*clk b
Inputs: b; Outputs: x
Showing rising clock on every transition: cluttered
Make implicit -- assume every edge has rising clock, even if not shown
What if we wanted a transition without a rising edge
We don’t consider such asynchronous FSMs -- less common, and advanced topic
Only consider synchronous FSMs -- rising edge on every transition
On2
On1
On3
Off
x=1
x=0 b ’
Inputs: b; Outputs: x a
Note: Transition with no associated condition thus transistions to next state on next clock cycle

31. FSM Definition FSM consists of
Set of states
Ex: {Off, On1, On2, On3}
Set of inputs, set of outputs
Ex: Inputs: {x}, Outputs: {b}
Initial state
Ex: “Off”
Set of transitions
Describes next states
Ex: Has 5 transitions
Set of actions
Sets outputs while in states
Ex: x=0, x=1, x=1, and x=1
Inputs: b; Outputs: x
On2
On1
On3
Off
x=1
x=0 b ’
We often draw FSM graphically, known as state diagram
Can also use table (state table), or textual languages

32. Standard Controller Architecture
How implement FSM as sequential circuit?
Use standard architecture
State register -- to store the present state
Combinational logic -- to compute outputs, and next state
For laser timer FSM
2-bit state register, can represent four states
Input b, output x
Known as controller
On2
On1
On3
Off
x=1
x=0 b ’
Inputs: b; Outputs: x
Combinational
logic
State register s1 s0 n1 n0 x b
clk
FSM
outputs
inputs
General version
Combinational
logic S m N O I
clk
m-bit
state register
FSM
outputs
inputs a

33. Finite-State Machines (FSMs)—Sequential Behavior
Finite-state machine (FSM) is a common model of sequential behavior
Example: If B=1, hold X=1 for 3 clock cycles
Note: Transitions implicitly ANDed with rising clock edge
Implementation model has two parts:
State register
Combinational logic
HDL model will reflect those two parts
Inputs: B; Outputs: X
X=0
Off B B
X=1
X=1
X=1
On1
On2
On3
FSM
inputs B X
outputs
FSM
Combinational
logic
State
Clk
State register
StateNext

34. Finite-State Machines (FSMs)—Sequential Behavior Modules with Multiple Procedures and Shared Variables
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
reg [1:0] State, StateNext;
// CombLogic
B) begin
case (State)
S_Off: begin
X <= 0;
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
...
...
S_On1: begin
X <= 1;
StateNext <= S_On2;
end
S_On2: begin
StateNext <= S_On3;
S_On3: begin
StateNext <= S_Off;
endcase
// StateReg
Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
endmodule
Inputs: B; Outputs: X
On2
On1
On3
Off
X=1
X=0 B
Combinational
logic
State register
State X B
Clk
FSM
inputs
outputs
StateNext
Code will be explained on following slides
vldd_ch3_LaserTimerBeh.v

35. Finite-State Machines (FSMs)—Sequential Behavior
Modules has two procedures
One procedure for combinational logic
One procedure for state register
But it's still a behavioral description
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
reg [1:0] State, StateNext;
// CombLogic
B) begin
...
end
// StateReg
Clk) begin
endmodule
FSM
inputs B X
FSM
outputs
Combinational
logic
State
Clk
State register
StateNext
vldd_ch3_LaserTimerBeh.v

36. Finite-State Machines (FSMs)—Sequential Behavior Parameters
parameter declaration
Not a variable or net, but rather a constant
A constant is a value that must be initialized, and that cannot be changed within the module’s definition
Four parameters defined
S_Off, S_On1, S_On2, S_On3
Correspond to FSM’s states
Should be initialized to unique values
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
reg [1:0] State, StateNext;
// CombLogic
B) begin
...
end
// StateReg
Clk) begin
endmodule
vldd_ch3_LaserTimerBeh.v

37. Finite-State Machines (FSMs)—Sequential Behavior
Module declares two reg variables
State, StateNext
Each is 2-bit vector (need two bits to represent four unique state values 0 to 3)
Variables are shared between CombLogic and StateReg procedures
CombLogic procedure
Event control sensitive to State and input B
Will output StateNext and X
StateReg procedure
Sensitive to Clk input
Will output State, which it stores
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
reg [1:0] State, StateNext;
// CombLogic
B) begin
...
end
// StateReg
Clk) begin
endmodule
Combinational
logic
State register
State X B
Clk
FSM
inputs
outputs
StateNext
vldd_ch3_LaserTimerBeh.v

38. Finite-State Machines (FSMs)—Sequential Behavior Procedures with Case Statements
Procedure may use case statement
Preferred over if-else-if when just one expression determines which statement to execute
case (expression)
Execute statement whose case item expression value matches case expression
case item expression : statement
statement is commonly a begin-end block, as in example
First case item expression that matches executes; remaining case items ignored
If no item matches, nothing executes
Last item may be "default : statement"
Statement executes if none of the previous items matched
// CombLogic
B) begin
case (State)
S_Off: begin
X <= 0;
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
X <= 1;
StateNext <= S_On2;
S_On2: begin
StateNext <= S_On3;
S_On3: begin
endcase
vldd_ch3_LaserTimerBeh.v

39. Finite-State Machines (FSMs)—Sequential Behavior Procedures with Case Statements
FSM’s CombLogic procedure
Case statement describes states
case (State)
Executes corresponding statement (often a begin-end block) based on State's current value
A state's statements consist of
Actions of the state
Setting of next state (transitions)
Ex: State is S_On1
Executes statements for state On1, jumps to endcase
reg [1:0] State, StateNext;
// CombLogic
B) begin
case (State)
S_Off: begin
X <= 0;
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
X <= 1;
StateNext <= S_On2;
S_On2: begin
StateNext <= S_On3;
S_On3: begin
endcase
Suppose State is S_On1
Inputs: X; Outputs: B
On2
On1
On3
Off
X=1
X=0 B' B
vldd_ch3_LaserTimerBeh.v

40. Finite-State Machines (FSMs)—Sequential Behavior
FSM StateReg Procedure
Similar to 4-bit register
Register for State is 2-bit vector reg variable
Procedure has synchronous reset
Resets State to FSM’s initial state, S_Off
...
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
reg [1:0] State, StateNext;
// StateReg
Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
vldd_ch3_LaserTimerBeh.v

41. Finite-State Machines (FSMs)—Sequential Behavior Modules with Multiple Procedures and Shared Variables
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 0, S_On1 = 1,
S_On2 = 2, S_On3 = 3;
reg [1:0] State, StateNext;
// CombLogic
B) begin
case (State)
S_Off: begin
X <= 0;
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
...
...
S_On1: begin
X <= 1;
StateNext <= S_On2;
end
S_On2: begin
StateNext <= S_On3;
S_On3: begin
StateNext <= S_Off;
endcase
// StateReg
Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
endmodule
Inputs: B; Outputs: X
On2
On1
On3
Off
X=1
X=0 B
Combinational
logic
State register
State X B
Clk
FSM
inputs
outputs
StateNext
Code should now be clear
vldd_ch3_LaserTimerBeh.v

42. Finite-State Machines (FSMs)—Sequential Behavior Self-Checking Testbenches
...
// Clock Procedure
always begin
Clk_s <= 0;
#10;
Clk_s <= 1;
end // Note: Procedure repeats
// Vector Procedure
initial begin
Rst_s <= 1;
B_s <= 0;
@(posedge Clk_s);
#5 Rst_s <= 0;
#5 B_s <= 1;
#5 B_s <= 0;
end
endmodule
FSM testbench
First part of file (variable/net declarations, module instantiations) similar to before
Vector Procedure
Resets FSM
Sets FSM's input values (“test vectors”)
Waits for specific clock cycles
We observe the resulting waveforms to determine if FSM behaves correctly
B_s
X_s
time (ns) 10 20 30 40
Clk_s 50 70
Rst_s 60 80 90
110
100
vldd_ch3_LaserTimerTB.v

43. Finite-State Machines (FSMs)—Sequential Behavior Self-Checking Testbenches
Reading waveforms is error-prone
Create self-checking testbench
Use if statements to check for expected values
If a check fails, print error message
Ex: if X_s fell to 0 one cycle too early, simulation might output:
95: Third X=1 failed
// Vector Procedure
initial begin
Rst_s <= 1;
B_s <= 0;
@(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Reset failed", $time);
Rst_s <= 0;
#5 B_s <= 1;
#5 B_s <= 0;
if (X_s != 1)
$display("%t: First X=1 failed", $time);
#5 if (X_s != 1)
$display("%t: Second X=1 failed", $time);
$display("%t: Third X=1 failed", $time);
$display("%t: Final X=0 failed", $time);
end
Clk_s
Rst_s
B_s
X_s 10 20 30 40 50 60 70 80 90
100
110
time (ns)
vldd_ch3_LaserTimerTBDisplay.v

44. Finite-State Machines (FSMs)—Sequential Behavior $display System Procedure
$display – built-in Verilog system procedure for printing information to display during simulation
A system procedure interacts with the simulator and/or host computer system
To write to a display, read a file, get the current simulation time, etc.
Starts with $ to distinguish from regular procedures
String argument is printed literally...
$display("Hello") will print "Hello"
Automatically adds newline character
...except when special sequences appear
%t: Display a time expression
Time expression must be next argument
$time – Built-in system procedure that returns the current simulation time
95: Third X=1 failed
// Vector Procedure
initial begin
Rst_s <= 1;
B_s <= 0;
@(posedge Clk_s);
#5 if (X_s != 0)
$display("%t: Reset failed", $time);
Rst_s <= 0;
#5 B_s <= 1;
#5 B_s <= 0;
if (X_s != 1)
$display("%t: First X=1 failed", $time);
#5 if (X_s != 1)
$display("%t: Second X=1 failed", $time);
$display("%t: Third X=1 failed", $time);
$display("%t: Final X=0 failed", $time);
end
vldd_ch3_LaserTimerTBDisplay.v

45. Controller Example: Button Press Synchronizerbi bo
Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed
We assumed such an ideal button press signal in earlier example, like the button in the laser timer controller

46. Controller Example: Button Press Synchronizer (cont)
Step 2: Create architecture
Combinational
logic n0 s1 s0 n1 bo bi
clk
State register
FSM
inputs
outputs
Step 1: FSM A B C
bo=1
bo=0 bi b i ’
FSM inputs: bi; FSM outputs: bo
Step 5: Create combinational circuit
clk
State register
outputs bo bi s1 s0 n1 n0
Combinational logic
n1 = s1’s0bi + s1s0bi
n0 = s1’s0’bi
bo = s1’s0bi’ + s1’s0bi = s1s0 a
Step 4: State table
FSM
Step 3: Encode states 00 01 10
bo=1
bo=0 bi ’
FSM inputs: bi; FSM outputs: bo
Step 5: Create combinational circuit

47. Controller Example: Sequence Generator
Want generate sequence 0001, 0011, 1100, 1000, (repeat)
Each value for one clock cycle
Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”
Step 2: Create architecture
Combinational
logic n0 s1 s0 n1
clk
State register w x y z
Step 1: Create FSM A B D
wxyz=0001
wxyz=1000
wxyz=0011
wxyz=1100 C
Inputs: none; Outputs: w,x,y,z A B D
wxyz=0001
wxyz=1000
wxyz=0011
wxyz=1100 C
Inputs: none; Outputs: w,x,y,z
Step 3: Encode states 00 01 10 11
clk
State register w x y z
FSM outputs n0 s0 s1 n1
Step 4: Create state table
w = s1
x = s1s0’
y = s1’s0
z = s1’
n1 = s1 xor s0
n0 = s0’ a
Step 5: Create combinational circuit

48. Controller Example: Sequence Generator
Want generate sequence 0001, 0011, 1100, 1000, (repeat)
Each value for one clock cycle
Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”
Step 2: Create architecture
Combinational
logic n0 s1 s0 n1
clk
State register w x y z
Step 1: Create FSM A B D
wxyz=0001
wxyz=1000
wxyz=0011
wxyz=1100 C
Inputs: none; Outputs: w,x,y,z A B D
wxyz=0001
wxyz=1000
wxyz=0011
wxyz=1100 C
Inputs: none; Outputs: w,x,y,z
Step 3: Encode states 00 01 10 11
clk
State register w x y z
FSM outputs n0 s0 s1 n1
Step 4: Create state table
w = s1
x = s1s0’
y = s1’s0
z = s1’
n1 = s1 xor s0
n0 = s0’ a
Step 5: Create combinational circuit

49. FSM Example: Secure Car Key (cont.)
Nice feature of FSM
Can evaluate output behavior for different input sequence
Timing diagrams show states and output values for different input waveforms K1 K2 K3 K4
r=1
r=0 W
ait I
nputs: a ; O
utputs: r ’
Q: Determine states and r value for given input waveform: W
ait K1 K2 K3 K4
clk I
nputs O
utputs S t a e r
clk I
nputs a W
ait K1 K2 K3 K4
Output
State r K1 a

50. Controller Example: Secure Car Key
(from earlier example) K1 K2 K3 K4
r=1
r=0
Wait
Inputs: a; Outputs: r a ’
Step 1
Step 4 a
Combinational
logic s2 s1 s0 n2 r a n1 n0
clk
State register
FSM
inputs
outputs
Step 2
FSM a ’
r=0
r=1
000
001
010
011
100 I
nputs: ; O
utputs: r
Step 3
We’ll omit Step 5

51. FSM Example: Code Detector
Unlock door (u=1) only when buttons pressed in sequence:
start, then red, blue, green, red
Input from each button: s, r, g, b
Also, output a indicates that some colored button pressed
FSM
Wait for start (s=1) in “Wait”
Once started (“Start”)
If see red, go to “Red1”
Then, if see blue, go to “Blue”
Then, if see green, go to “Green”
Then, if see red, go to “Red2”
In that state, open the door (u=1)
Wrong button at any step, return to “Wait”, without opening door s
Start u r
Door
Red
Code g
lock a
Green
detector b
Blue a
Wait
Start
Red1 R
ed2
Green
Blue s ’ a r b g ab ag ar
u=0
u=1
Inputs: s,r,g,b,a;
Outputs: u a
Q: Can you trick this FSM to open the door, without knowing the code? a
A: Yes, hold all buttons simultaneously

52. Improve FSM for Code Detector
Inputs: s,r,g,b,a;
Outputs: u
Wait s’
ar’
ab’
ag’
ar’
u=0 a s
Start a ’
u=0 ar ab ag ar
Red1
Blue
Green
Red2 a ’ a ’ a ’
u=0
u=0
u=0
u=1
Note: small problem still remains; we’ll discuss later
New transition conditions detect if wrong button pressed, returns to “Wait”
FSM provides formal, concrete means to accurately define desired behavior

53. Common Pitfalls Regarding Transition Properties
Only one condition should be true
For all transitions leaving a state
Else, which one?
One condition must be true
Else, where go? a

54. Verifying Correct Transition Properties
Can verify using Boolean algebra
Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0  proves pair can never simultaneously be true
One condition true: OR of all conditions of transitions leaving a state) should equal 1  proves at least one condition must be true
Example
a * a’b
= (a * a’) * b
= 0 * b
= 0
OK!
Answer: a
a + a’b
= a*(1+b) + a’b
= a + ab + a’b
= a + (a+a’)b
= a + b
Fails! Might not be 1 (i.e., a=0, b=0)
Q: For shown transitions, prove whether:
* Only one condition true (AND of each pair is always 0)
* One condition true (OR of all transitions is always 1)

55. Evidence that Pitfall is Common
Recall code detector FSM
We “fixed” a problem with the transition conditions
Do the transitions obey the two required transition properties?
Consider transitions of state Start, and the “only one true” property
Wait s ’
u=0 s a
Start a ’
u=0 ar ab ag ar
Red1
Blue
Green
Red2 a ’ a ’ a ’
u=0
u=0
u=0
u=1
ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g)
= (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g) = (a*a)*r*(r’+b+g) = a*r*(r’+b+g)
= 0 = 0 = arr’+arb+arg
= 0 + arb+arg
= arb + arg
= ar(b+g)
Fails! Means that two of Start’s transitions could be true
Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken?
Q: How to solve? a
A: ar should be arb’g’
(likewise for ab, ag, ar)
Note: As evidence the pitfall is common,
we admit the mistake was not intentional.
A reviewer of the book caught it.

56. Simplifying Notations
FSMs
Assume unassigned output implicitly assigned 0
Sequential circuits
Assume unconnected clock inputs connected to same external clock a

57. More on Flip-Flops and Controllers
3.5
More on Flip-Flops and Controllers
Other flip-flop types
SR flip-flop: like SR latch, but edge triggered
JK flip-flop: like SR (SJ, RK)
But when JK=11, toggles
10, 01
T flip-flop: JK with inputs tied together
Toggles on every rising clock edge
Previously utilized to minimize logic outside flip-flop
Today, minimizing logic to such extent is not as important
D flip-flops are thus by far the most common

58. Non-Ideal Flip-Flop Behavior
Can’t change flip-flop input too close to clock edge
Setup time: time that D must be stable before edge
Else, stable value not present at internal latch
Hold time: time that D must be held stable after edge
Else, new value doesn’t have time to loop around and stabilize in internal latch
Setup time violation
Leads to oscillation!

59. Metastability
Violating setup/hold time can lead to bad situation known as metastable state
Metastable state: Any flip-flop state other than stable 1 or 0
Eventually settles to one or other, but we don’t know which
For internal circuits, we can make sure observe setup time
But what if input comes from external (asynchronous) source, e.g., button press?
Partial solution
Insert synchronizer flip-flop for asynchronous input
Special flip-flop with very small setup/hold time
Doesn’t completely prevent metastability a

60. Metastability One flip-flop doesn’t completely solve problem
How about adding more synchronizer flip-flops?
Helps, but just decreases probability of metastability
So how solve completely?
Can’t! May be unsettling to new designers. But we just can’t guarantee a design that won’t ever be metastable. We can just minimize the mean time between failure (MTBF) -- a number often given along with a circuit
Probability of flip-flop being metastable is…
very
very
very
incredibly l o w
low
low l o w ai
synchronizers

61. Flip-Flop Set and Reset Inputs
Some flip-flops have additional inputs
Synchronous reset: clears Q to 0 on next clock edge
Synchronous set: sets Q to 1 on next clock edge
Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge)
Example timing diagram shown
Asynchronous set: set Q to 1 immediately

62. Initial State of a Controller
All our FSMs had initial state
But our sequential circuit designs did not
Can accomplish using flip-flops with reset/set inputs
Shown circuit initializes flip-flops to 01
Designer must ensure reset input is 1 during power up of circuit
By electronic circuit design
Inputs: x; Outputs: b
x=0
Off b ’ b
x=1
x=1
x=1
On1
On2
On3 D Q ’ R S
State register
clk
reset s1 s0 n0 n1 b x
Combinational
logic

63. Top-Down Design – FSMs to Controller Structure

64. Top-Down Design – FSMs to Controller Structure
Capture behavior
Simulate
W_s
P_s
S_s
K_s
Capture structure
Should be the same
Recall from Chapter 2
Top-down design
Capture behavior, and simulate
Capture structure (circuit), simulate again
Gets behavior right first, unfettered by complexity of creating structure
Capture behavior: FSM
Capture structure: Controller
Create architecture (state register and combinational logic)
Encode states
Create stable table (describes combinational logic)
Implement combinational logic
Combinational
logic
State register S1 S0 N1 N0 X B
Clk
FSM
outputs
inputs
X=1
X=0 B B' 01 00 10 11
On2
On1 O ff
On3
Inputs: B; Outputs: X
LaserTimer example

65. Top-Down Design – FSMs to Controller Structure
outputs
FSM
Recall from Chapter 2
Top-down design
Capture behavior, and simulate
Capture structure (circuit), simulate again
Gets behavior right first, unfettered by complexity of creating structure
Capture behavior: FSM
Capture structure: Controller
Create architecture (state register and combinational logic)
Encode states
Create stable table (describes combinational logic)
Implement combinational logic
X=1
X=0 B B' 01 00 10 11
On2
On1 O ff
On3
Inputs: B; Outputs: X

66. Top-Down Design – FSMs to Controller Structure
outputs
FSM
Recall from Chapter 2
Top-down design
Capture behavior, and simulate
Capture structure (circuit), simulate again
Gets behavior right first, unfettered by complexity of creating structure
Capture behavior: FSM
Capture structure: Controller
Create architecture (state register and combinational logic)
Encode states
Create stable table (describes combinational logic)
Implement combinational logic
X=1
X=0 B B' 01 00 10 11
On2
On1 O ff
On3
Inputs: B; Outputs: X
X = S1 + S0
N1 = S1’S0 + S1S0’
N0 = S1’S0’B + S1S0’

67. Controller Structure Structural description Test with LaserTimerTB
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 2'b00;
reg [1:0] State, StateNext;
// State encodings:
// S_Off 00, S_On1 01, S_On2 10, S_On3 11
// CombLogic
B) begin
X <= State[1] | State[0];
StateNext[1] <= (~State[1] & State[0])
| (State[1] & ~State[0]);
StateNext[0] <= (~State[1] & ~State[0] & B)
end
// StateReg
Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
endmodule
outputs
FSM
Structural description
Test with LaserTimerTB
Same results
X = S1 + S0
N1 = S1’S0 + S1S0’
N0 = S1’S0’B + S1S0’
Combinational
logic
State register S1 S0 N1 N0 X B
Clk
FSM
outputs
inputs
B_s
X_s
time (ns) 10 20 30 40
Clk_s 50 70
Rst_s 60 80 90
110
100
vldd_ch3_LaserTimerStruct.v

68. Controller Structure Initial state is S_Off
`timescale 1 ns/1 ns
module LaserTimer(B, X, Clk, Rst);
input B;
output reg X;
input Clk, Rst;
parameter S_Off = 2'b00;
reg [1:0] State, StateNext;
// State encodings:
// S_Off 00, S_On1 01, S_On2 10, S_On3 11
// CombLogic
B) begin
X <= State[1] | State[0];
StateNext[1] <= (~State[1] & State[0])
| (State[1] & ~State[0]);
StateNext[0] <= (~State[1] & ~State[0] & B)
end
// StateReg
Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
endmodule
outputs
FSM
Initial state is S_Off
Encoded as "00"
State register set to S_Off during FSM reset
Note that CombLogic uses equations, not case statement
Actually CombLogic is still behavioral
Do top-down design again, this time on CombLogic, to get structure
vldd_ch3_LaserTimerStruct.v

69. Common Pitfall: Not Assigning Every Output in Every State
FSM outputs should be combinational function of current state (for Moore FSM)
Not assigning output in given state means previous value is remembered
Output has memory
Behavior is not an FSM
Solution 1
Be sure to assign every output in every state
Solution 2
Assign default values before case statement
Later assignment in state overwrites default
// CombLogic
B) begin
X <= 0;
case (State)
S_Off: begin
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
X <= 1;
StateNext <= S_On2;
S_On2: begin
StateNext <= S_On3;
S_On3: begin
endcase
Could delete this without changing behavior (but probably clearer to keep it)

70. Common Pitfall: Not Assigning Every Output in Every State
Solution 2
Assign default values before case statement
Later assignment in state overwrites default
Helps clarify which actions are important in which state
Corresponds directly to the common simplifying FSM diagram notation of implicitly setting unassigned outputs to 0
case State
S: begin
A <= 0;
B <= 1;
C <= 0;
end
T: begin
B <= 0;
C <= 1;
endcase S T
A=0
A=0
B=1
B=0
C=0
C=1
A <= 0;
B <= 0;
C <= 0;
case State
S: begin
B <= 1;
end
T: begin
C <= 1;
endcase S T
B=1
C=1

71. More Simulation Concepts

72. The Simulation Cycle
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Instructive to consider how an HDL simulator works
HDL simulation is complex; we'll introduce simplified form
Consider example SimEx1
Three reg variables – Q, Clk, S
Three procedures – P1, P2, P3
Simulator's job: Determine values for nets and variables over time
Repeatedly executes and suspends procedures
Note: Actually considers more objects, known collectively as processes, but we'll keep matters simple here to get just the basic idea of simulation
Maintains a simulation time Time
vldd_ch3_SimEx1.v

73. We'll use arrow to show where a procedure stops
The Simulation Cycle
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Start of simulation
Simulation time Time is 0
Bit variables/nets initialized to the unknown value x
Execute each procedure
In any order, until stops at a delay or event control
We'll use arrow to show where a procedure stops P1
Clk <= 0, then stop.
Activate when Time is 0+10=10 ns.
Procedures P2
No actions, then stop.
Activate when S changes. P3
No actions, then stop.
Activate when Clk changes to 1
Time (ns): x
Start x Q
Variables
Clk S
vldd_ch3_SimEx1.v

74. The Simulation Cycle Simulation cycle P1 Activate when Time is 10 ns.
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Simulation cycle
Set time to next time at which a procedure activates (note: could be same as current time)
In this case, time = 10 ns (P1 activates)
Execute active procedures (in any order) until stops P1
Activate when Time is 10 ns.
Clk <= 1, stop, activate when Time=10+10=20 ns.
Procedures P2
Activate when S changes. P3
Activate when Clk changes to 1.
Time (ns):
Start x 1 10 Q x x
Variables
Clk x S x x
vldd_ch3_SimEx1.v

75. The Simulation Cycle Simulation cycle
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Simulation cycle
Set time to next time at which a procedure activates
Still 10 ns; Clk just changed to 1 (P3 activates)
Execute active procedures (in any order) until stops P1
Activate when Time is 20 ns.
Procedures P2
Activate when S changes. P3
Activate when Clk changes to 1
S <= 1, stop, activate when Clk changes to 1 again
Time (ns):
Start 10 x 1 10 Q x x x
Variables
Clk x 1 S x x x
vldd_ch3_SimEx1.v

76. The Simulation Cycle Simulation cycle
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Simulation cycle
Set time to next time at which a procedure activates
Still 10 ns; S just changed (P2 activates)
Execute active procedures until stops P1
Activate when Time is 20 ns.
Procedures P2
Activate when S changes.
Q <= 0 (~S), stop, activate when S changes. P3
Activate when change on Clk to 1.
Time (ns):
Start 10 10 1 10 Q x x x x
Variables
Clk x 1 1 S x x x 1
vldd_ch3_SimEx1.v

77. The Simulation Cycle Simulation cycle
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Simulation cycle
Set time to next time at which a procedure activates
In this case, set Time = 20 ns (P1 activates)
Execute active procedures until stops P1
Activate when Time is 20 ns.
Clk <= 0, stop, activate when T=20+10=30ns.
Procedures P2
Activate when S changes. P3
Activate when change on Clk to 1.
Time (ns):
Init 10 10 1 10 1 20 Q x x x x
Variables
Clk x 1 1 S x x x 1
vldd_ch3_SimEx1.v

78. The Simulation Cycle
`timescale 1 ns/1 ns
module SimEx1(Q);
output reg Q;
reg Clk, S;
// P1
always begin
Clk <= 0;
#10;
Clk <= 1;
end
// P2
begin
Q <= ~S;
// P3
initial begin
@ (posedge Clk);
S <= 1;
S <= 0;
endmodule
Simulation ends when user-specified time is reached
Variable/net values translate to waveforms Q
Clk S
Variables
Time (ns) 10 20 30 40 50 x
Time (ns):
Init 10 10 10 20 1 30 1 30 1 30 1 40 1 50 Q x x x x
Variables
Clk x 1 1 1 S x x x 1 1 1
vldd_ch3_SimEx1.v

79. Variable Updates Simulation cycle (revised)
Set time to next time at which a procedure resumes
Execute active procedures
Update variables with schedule values
Assignment using "<=" ("non blocking assignment") doesn't change variable's value immediately
Instead, schedules a change of value by placing an event on an event queue
Scheduled changes occur at end of simulation cycle
Important implications
Procedure execution order in a simulation cycle doesn't matter
Assume procedures 1 and 2 are both active
Proc1 schedules B to be 1, but does not change the present value of B. B is still 0.
Proc2 schedules A to be 0 (the present value of B).
At end of simulation cycle, B is updated to 1 and A to 0
Order of assignments to different variables in a procedure doesn't matter
Assume C was 0. Scheduled values will be C=1 and D=0, for either Proc3a or Proc3b.
Later assignment in procedure effectively overwrites earlier assignment
E will be updated with 0, but then by 1; so E is 1 at the end of the simulation cycle.
Assume B is 0. Proc1:
B <= ~B;
Proc2:
A <= B;
A will be 0, not 1.
Proc3a:
C <= ~C;
D <= C;
Same
Proc3b:
D <= C;
C <= ~C;
Proc4:
E <= 0;
...
E <= 1;
Recall FSM output assignment example, in which default assignments were added before the case statement.

80. Resets

81. Resets Reset – Behavior of a register when a reset input is asserted3 I 2 I 1 I
Reset – Behavior of a register when a reset input is asserted
Good practice dictates having defined reset behavior for every register
Reset behavior should always have priority over normal register behavior
Reset behavior
Usually clears register to 0s
May initialize to other value
e.g., state register of a controller may be initialized to encoding of initial state of FSM
Reset usually asserted externally at start of sequential circuit operation, but also to restart due to failure, user request, or other reason
reg(4)
Rst Q3 Q2 Q1 Q0
`timescale 1 ns/1 ns
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
input Clk, Rst;
Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule
vldd_ch3_Reg4.v

82. Synchronous Reset Previous examples used synchronous resets3 I 2 I 1 I
Previous examples used synchronous resets
Rst input only considered during rising clock
reg(4)
Rst Q3 Q2 Q1 Q0
`timescale 1 ns/1 ns
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
input Clk, Rst;
Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule
Rst
Clk Q I
xxxx
Rst=1 has no effect until rising clock
vldd_ch3_Reg4.v

83. Asynchronous Reset Can also use asynchronous resetI 3 I 2 I 1 I
Can also use asynchronous reset
Rst input considered independently from clock
Add "posedge Rst" to sensitivity list
reg(4)
Rst Q3 Q2 Q1 Q0
`timescale 1 ns/1 ns
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;
input Clk, Rst;
Clk, posedge Rst) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
endmodule
Rst
Clk Q I
Asynchronous reset
Rst=1 has almost immediate effect
Rst
Clk Q I
xxxx
Synchronous reset
Rst=1 has no effect until next rising clock
vldd_ch3_Reg4AsyRst.v

84. Asynchronous Reset
Could have used asynchronous reset for FSM state register too
...
// StateReg
Clk) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
Synchronous
...
// StateReg
Clk, posedge Rst) begin
if (Rst == 1 )
State <= S_Off;
else
State <= StateNext;
end
Asynchronous
vldd_ch3_LaserTimerBehAsyRst.v

85. Synchronous versus Asynchronous Resets
Which is better – synchronous or asynchronous reset?
Hotly debated in design community
Each has pros and cons
e.g., asynchronous can still reset even if clock is not functioning, synchronous avoids timing analysis problems sometimes accompanying asynchronous designs
We won’t try to settle the debate here
What’s important is to be consistent throughout a design
All registers should have defined reset behavior that takes priority over normal register behavior
That behavior should all be synchronous reset or all be asynchronous reset
We will use synchronous resets in all of our remaining examples

86. Describing Safe FSMs

87. Describing Safe FSMs
Safe FSM – If enters illegal state, transitions to a legal state
Example
Suppose example has only three states
Two-bit encoding has illegal state encoding "11"
Also known as "unreachable" state
Not possible to enter that state under normal FSM operation
But actually possible to enter that state due to circuit error – e.g., electrical noise that causes state register bit to switch
Inputs: B; Outputs: X
X=0 00 B' O ff B
X=1
X=1 01
On1 10
On2

88. Describing Safe FSMs
Safe FSM – If enters illegal state, transitions to a legal state
Example
Suppose example has only three states
Two-bit encoding has illegal state encoding "11"
Safe implementation
Transition to appropriate legal state
Even though that undefined state appears to be unreachable
Thus, FSM recovers from the error
Inputs: B; Outputs: X
X=0
X=0 11 00 B' O ff B
X=1
X=1 01
On1 10
On2

89. Describing Safe FSMs in Verilog HDL
...
reg [1:0] State, StateNext;
B) begin
case (State)
S_Off: begin
X <= 0;
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
X <= 1;
StateNext <= S_On2;
S_On2: begin
endcase
Unsafe FSM description
Only describes legal states, ignores illegal states
Some synthesis tools support "safe" option during synthesis
Automatically creates safe FSM from an unsafe FSM description

90. Describing Safe FSMs in Verilog HDL
...
reg [1:0] State, StateNext;
B) begin
case (State)
S_Off: begin
X <= 0;
if (B == 0)
StateNext <= S_Off;
else
StateNext <= S_On1;
end
S_On1: begin
X <= 1;
StateNext <= S_On2;
S_On2: begin
default: begin
endcase
Explicitly describing a safe FSM
Include case item(s) to describe illegal states
Can use "default" case item
Executes if State equals anything other than S_Off, S_On1, or S_On2
Note: Use of default is wise regardless of number of states
Even if number is power of two, because state encoding may use more than minimum number of bits
e.g., one-hot encoding has many more illegal states than legal states
Note: If synthesis tool support "safe" option, use it
Otherwise, tool may automatically optimize away unreachable states to improve performance and size, but making state machine unsafe
vldd_ch3_LaserTimerBehSafe.v