1. Inter TEL62 communication M. Raggi, M. Piccini, F. Gonnella 16 th October 2013 TDAQ Working Group Meeting

2. Why inter TEL62 communication  Needed in the LAV and RICH to merge primitive information before sending them to L0TP  12 Tel62 primitive to be merged in one over 100m beam line  4 Tel62 information to be merged into the same crate.  Different solution possible  Eth gigabit  Simple LVDS transmitter: serializer  Couple of meeting during last month to find an approach which fits requirements of both detectors 16 October 2013M. Raggi - LNF2

3. The RICH problem  The RICH has 2000 channels, readout by 4 TEL62 (16 TDCB)  The main issue is to have a unique L0 primitive coming out  Collect the information from the RICH 4 half spots  Transparent mode approach: just move all the data to the end  Merging mode approach: build pre-primitive on the road  Estimated data throughput for the RICH  900 Mbit/s Trasparent mode (see M. Piccini @ Liverpool)  400 Mbit/s Merging mode (see M. Piccini @ Liverpool) 16 October 2013M. Raggi - LNF3

4. The LAV problem  The LAV has 2500 channels on 12 TEL62 in 12 different station  Expected rates mainly from muon halo (TDR)  Total rate 11.2 MHz  OR rate 4.13 MHz  Collect the information from the 12 LAV station  Transparent mode approach: just move all the data to the LAV12  Merging mode approach : merge muon on the road  Estimated data throughput for the LAV  723 Mbit/s Trasparent mode  262 Mbit/s Merging mode 16 October 2013M. Raggi - LNF4

5. Serializer solution 16 October 2013M. Raggi - LNF5

6. Serializer model DS92LV16  LVDS Serializer/Deserializer 25 - 80 MHz  25–80 MHz 16:1/1:16 Serializer/Deserializer  2.56Gbps Full Duplex Throughput  Independent Transmitter and Receiver  Operation with separate Clock, Enable, Power  Single +3.3V Power Supply 100+120 mA  Internal PLL  Transmission length depending on cable only  In the 80MHz operation mode can transmit a primitive of 64 bits in 50ns 4 clock cycles  Total throughput=16bit*80MHz=1.28Gbit/s 16 October 2013M. Raggi - LNF6

7. On the TEL62 side J25 60 pins 16 October 2013M. Raggi - LNF7 TEL62 connector Connection to SL  TEL62 connector  3.3V power line  Jtag connection  Connection to SL  2x16bits data bus  2 data valid lines  2 clock connections  Aux board Reset

8. Mezzanine block diagram 16 October 2013M. Raggi - LNF8 data to SL bit Data to SL bit Deserializer Serializer J25 to TEL62 Out In  Work flow in the daisy chain mode  Get input on single LVDS pair and deserialize it to the 16 bit bus to SL FPGA  Read data in the SL into a fifo (eventually add new primitive)  Copy the last word on the fifo into the data bus on the mezzanine  Serialize the data bus on the 1 single pair LVDS cable to next TEL62  The block diagram shows 2 chips for better logical separation of tasks but in fact 1 chip can do both the function at the same time 60 pins

9. Estimated time delays  For the LAV the delay depends on the station in which the primitive is produced. In the worst hypothesis of primitive generation in ANTI-A1  Arrival delay to ANTI-A12 due to cables: 100m at 0.66c ~ 500ns  Arrival delay to ANTI-A12 due to mezzanine 11*50 ~ 550 ns  Total expected maximum delay is then ~ 1  s  Particle time of flight in 100m ~330 ns  For the RICH the only delay is due to writing on the fifo and in and out of the serializer  64 bit primitive needs 4 clock cycle to be written ~50ns*3TEL62 ~ 150ns  No delay due to cable (TEL62 in the same crate)  The values are well below the 1ms L0 latency 16 October 2013M. Raggi - LNF9

10. Conclusions  An first possible solution for the transmission between different TEL62 has been explored  Can profit by Perugia experience with serializer DS92LV16  Matches both detector requirements  Seem cheap and quite easy to implement  No show stopper have been identified so far  Mechanical issue on mezzanine support still not examined in detail 16 October 2013M. Raggi - LNF10

11. Thank you for your attention 16 October 2013 11