1. IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2006 - All rights reserved LEON-2: General Purpose Processor for a Wireless Engine Z. Stamenković

2. IHP Innovations for High Performance MicroelectronicsSlide 2© 2006 - All rights reserved Concept To realize a vertical strategy from application to silicon Application Location Aware Service Platform picoJava Java VM Application Presentation Session Transport (TCP) Network (IP) Data Link Control Physical Management: Power consumption Performance

3. IHP Innovations for High Performance MicroelectronicsSlide 3© 2006 - All rights reserved Wireless Engine RF BasebandDLC Application Engine Protocol Engine Power Management Test Engine RF Baseband DLC Application Engine Protocol Engine Power Management Test Engine Vertical approach from application to silicon can significantly improve the inter-layer performance characteristics Wireless engine is a system-on-chip solution for mobile computing terminals based on the vertical approach

4. IHP Innovations for High Performance MicroelectronicsSlide 4© 2006 - All rights reserved Wireless Broadband Network (WBN) Single chip communication system for wireless data transfer in the 5GHz band with a rate of about 6 to 54 Mbit/s Wireless Internet (WI) Vertical protocol optimization: power efficiency, performance Mobile Computing (MoCo) Service platform: Location aware Java based Wireless Engine Projects PHY DLC IP TCP App Management

5. IHP Innovations for High Performance MicroelectronicsSlide 5© 2006 - All rights reserved CPU I-Cache D-Cache AHB Controller DCLDSU AHB AHB/APBBridg e Memory Controller APB SRAMFlash IO PortIrq Ctrl Timers UARTs LEON-2 Processor System

6. IHP Innovations for High Performance MicroelectronicsSlide 6© 2006 - All rights reserved Installation of the release Adaptation of the configuration tool (to include IHP’s library) Implementation of data and instruction caches Implementation of BIST logic for SRAMs Logic synthesis of the design Implementation of scan chain Generation of the chip layout Simulation (functional, post-synthesis and post-layout net-list) Scan test vectors generation (ATPG) BIST and scan test simulation Adaptation of testbenches (SPARC CC installed) EVCD test vectors generation (with and without timing data) Test specification Documentation Implementation of LEON-2 Processor System

7. IHP Innovations for High Performance MicroelectronicsSlide 7© 2006 - All rights reserved Chip Features