1. Khaled A. Al-Utaibi alutaibi@uoh.edu.sa
Memory Devices
Khaled A. Al-Utaibi

2. Agenda Introduction Memory Pin Connections ROM Memory RAM Memory
Memory Organization
Types of Memory Access
Data Alignment

3. Introduction There are two main types of memory:
(1) Read-Only Memory (ROM)
(2) Random Access Memory (RAM)
EPROM
DRAM
SRAM
EEPROM

4. Memory Pin Connections
Pin connections common to all memory devices are:
Address Lines
Data Lines
Selection Control
Read/Write Control
See Figure 1 for ROM and RAM generic-memory devices.

5. Figure 1: A pseudo-memory component illustrating the address, data, and control connections.

6. Memory Pin Connections Address Lines
All memory devices have address inputs that select a memory location within the memory device.
Address lines are labeled from A0, the least significant address input, to An-1 where n is the total number of address pins.
For example, a memory device with 10 address pins has its address pins labeled from A0 to A9.
The number of address pins found on a memory device is determined by the number of memory locations found within it.

7. Memory Pin Connections Address Lines
Today, the common memory devices have between 1K (1024) to 1G (1,073,741,824) memory locations, with 4G and larger memory location devices on the horizon.
A 1K memory device has 10 address pins (A0–A9); therefore, 10 address inputs are required to select any of its 1024 memory locations.
It takes a 10-bit binary number (1024 different combinations) to select any single location on a location device.

8. Memory Pin Connections Address Lines
If a memory device has 11 address connections (A0–A11), it has 2048 (2K) internal memory locations.
The number of memory locations can thus be extrapolated from the number of address pins.
For example, a 4K memory device has 12 address connections, an 8K device has 13, and so forth.
A device that contains 1M locations requires a 20-bit address (A0–A19).

9. Memory Pin Connections Data Lines
All memory devices have a set of data outputs or input/outputs.
The device illustrated in Figure 1 has a common set of input/output (I/O) lines.
Today, many memory devices have bidirectional common I/O pins.
The data lines are the points at which data are entered for storage or extracted for reading.
Data pins on memory devices are labeled D0 through D7 for an 8-bit-wide memory device.

10. Memory Pin Connections Selection Control
Each memory device has a control input – sometimes more than one – that selects or enables the memory device.
This type of input is most often called a Chip Select (CS), Chip Enable (CE), or simply Select (S) input.
If the CS, CE, or S input is active (a logic 0, in this case, because of the over bar), the memory device performs a read or write operation;
if it is inactive (a logic 1, in this case), the memory device cannot do a read or a write because it is turned off or disabled.
If more than one connection is present, all must be activated to read or write data.

11. Memory Pin Connections Read/Write Control
A ROM has an Output Enable (OE) or a Gate (G) connection, which allows data to flow out of the output data pins of the ROM.
If (OE) and the selection input (CE) are both active, the output is enabled;
if (OE) is inactive, the output is disabled at its high-impedance state.
The (OE) connection enables and disables a set of three-state buffers located within the memory device and must be active to read data.

12. Memory Pin Connections Read/Write Control
A RAM memory device has either one or two control inputs.
If there is only one control input, it is often called (R/W).
This pin selects a read operation or a write operation only if the device is selected by the selection input (CS).
If the RAM has two control inputs, they are usually labeled Write Enable (WE), and Output Enable (OE).

13. Memory Pin Connections Read/Write Control
The (WE) must be active to perform a memory write.
The (OE) must be active to perform a memory read.
When these two controls are present, they must never both be active at the same time.
If both control inputs are inactive (logic 1s), data are neither written nor read, and the data connections are at their high-impedance state.

14. ROM Memory Permanently stores data for the system.
Its contents do not change even if power is disconnected.
The most common used ROMs are:
Erasable Programmable ROM (EPROM)
Electrically Erasable Programmable ROM (EEPROM)
Flash
Flash
EEPROM
EPROM

15. ROM Memory EPROM
The EPROM (erasable programmable read-only memory) is commonly used when software must be changed often.
An EPROM is programmed on a device called an EPROM programmer.
Also erasable if exposed to high-intensity ultraviolet light.

16. ROM Memory EEPROM
EEPROM can be programmed and erased without removing the chip from its socket.
Both byte and bulk erasure modes are possible.
EEPROMs are changed 1 byte at a time, which makes them versatile but slow.

17. ROM Memory Flash Flash Memory overcomes this limitation of EEPROM
This device uses in-circuit wiring to erase by applying an electrical field to the entire chip or to predetermined sections of the chip called blocks.
It works much faster than EEPROMs because it writes data in chunks, usually 512 bytes in size, instead of 1 byte at a time.

18. RAM Memory RAM stands for random access memory.
This device retain data as long as DC power is applied.
Once the power is turned off all data stored in the RAM will be lost.
The main difference between ROM and RAM is that RAM is written under normal operation, whereas ROM is programmed outside the computer and normally is only read.
There are two main types of RAM:
(1) Static Random Access Memory (SRAM)
(2) Dynamic Random Access Memory (DRAM)

19. RAM Memory Static RAM (SRAM)
RAM devices retain data as long as DC power is applied (i.e. no special action is required to retain data).
Static RAM (SRAM) uses a flip-flop as the basic storage element.
A typical SRAM memory cell consists of 6 transistors connected as shown in the Figure 2 and its equivalent representation in Figure 3.

20. Static RAM (SRAM) Operation
To read the data stored by the SRAM cell:
The Row-select line is made active.
The voltage difference between Column and Column lines is sensed.
A positive voltage indicates a logic 1 is stored.
A negative voltage between these same lines indicates a logic 0 is stored.
To write data into the SRAM cell:
To store a logic 1, the Column line is driven high and the Column line is driven low
To store a logic 0, the process is repeated, but this time the Column line is driven low and Column high.

21. Figure 2: Implementation of a static RAM cell using 6 transistors.

22. Figure 3: Equivalent implementation of a static RAM cell using 6 transistors.

23. RAM Memory Dynamic RAM (DRAM)
A DRAM memory cell consists of a single transistor and a capacitor as shown in the Figure 4.
Thus, DRAM chips are much denser and can hold more data than SRAM in the same size package.
However, capacitors constantly leak electricity, which requires a memory controller to refresh the DRAM several times a second to maintain the data.
The DRAM cell can retain data for only 2 or 4 ms on its integrated capacitor.
After 2 or 4 ms, the content of the DRAM must be completely rewritten (refreshed).
The value stored in the cell is determined by the charge of the capacitor (Charged = logic 1, Discharged = logic 0)

24. Figure 4: Implementation of a dynamic RAM cell using 1 transistors.

25. RAM Memory Dynamic RAM (DRAM)
To read the data stored by the DRAM cell:
Pre-charge the bit line to Vcc/2.
Set the word line HIGH.
A sense amplifier is used to determine the logic store in the cell as follows:
If current flows into the cell  the cell is at logic
If current flows out of the cell  the cell is at logic
Cell contents are destroyed by the read!
Hence, the bit value must be written back after reading.

26. RAM Memory Dynamic RAM (DRAM)
To write data into the DRAM cell:
Set the word line HIGH.
To write logic 1 set the bit line HIGH
To write logic 0 set the bit line LOW
Set the select line LOW.
Note that the stored charge for a 1 will eventually leak off.
Typical devices require each cell to be refreshed once every 2 or 4 ms.

27. Memory Organization
The organization of a memory chip refers to the way in which its cells are arranged to provide external data access.
For example, a particular chip may have a total of 16 MB of storage.
Externally, however, these 16 Mb may be accessed in several different ways:
(1) 16M x 1 (Le., 16M bits)
(2) 4M x 4 (i.e., 4M nibbles)
(3) 2M x 8 (i.e., 2M bytes)
(4) 1M x 16 (Le. 16M words)

28. Memory Organization
SRAMs and ROMs are typically arranged as byte- wide (i.e. provide 8-bit external data access).
The organization of a memory chip is important because it determines how many chips will be required in a memory interface.

29. Memory Organization
Example 1: Using 64K x 8 SRAMs, determine the minimum number of chips required to construct a memory interface to each of the following processors. For each interface, calculate the total memory capacity provided.
(a) 8088
(b) 8086
(c) 80486
(d) Pentium

30. Memory Organization
Example 1: Using 64K x 8 SRAMs, determine the minimum number of chips required to construct a memory interface to each of the following processors. For each interface, calculate the total memory capacity provided.
(a) 8088
(b) 8086
(c) 80486
(d) Pentium

31. Types of Memory Access
Depending on the processor, the quantity of data transferred per memory cycle can be:
1 byte (the 8088)
2 bytes (the 8086)
4 bytes (the 386 and 486)
8 bytes (the Pentium/Pro)
D7-D0

32. Types of Memory Access
Depending on the processor, the quantity of data transferred per memory cycle can be:
1 byte (the 8088)
2 bytes (the 8086)
4 bytes (the 386 and 486)
8 bytes (the Pentium/Pro)

33. Types of Memory Access
Depending on the processor, the quantity of data transferred per memory cycle can be:
1 byte (the 8088)
2 bytes (the 8086)
4 bytes (the 386 and 486)
8 bytes (the Pentium/Pro)

34. Types of Memory Access
To indicate which bits of the data bus will be involved in the data transfer, the 80x86 processors provide byte enable output pins:
The 8086 (BHE)
The 386 & 486 (BE3-BE0)
The Pentium & Pentium Pro (BE7-BE0)

35. Types of Memory Access
To indicate which bits of the data bus will be involved in the data transfer, the 80x86 processors provide byte enable output pins:
The 8086 (BHE)
The 386 & 486 (BE3-BE0)
The Pentium & Pentium Pro (BE7-BE0)

36. Types of Memory Access
Using these byte enable signals, the 80x86 processors can indicate that:
(1) A single byte is to be transferred (only one byte enable signal active).
(2) A word is to be transferred (two byte enable signals active).
(3) A double-word is to be transferred (four byte enable signals active).
(4) A quad-word is to be transferred (all eight byte enable signals active).
Note that, when a memory transfer occurs, consecutive memory locations must be accessed,

37. Types of Memory Access
Example 2: Assume a Pentium processor executes the following instructions. Indicate the logic state of the BE7-BE0 byte enables for each associated memory access.
(a) MOV AL,[0000]
(b) MOV AX,[0000]
(c) MOV EAX,[0000]

38. Types of Memory Access
Example 2: Assume a Pentium processor executes the following instructions. Indicate the logic state of the BE7-BE0 byte enables for each associated memory access.
(a) MOV AL,[0000]
(b) MOV AX,[0000]
(c) MOV EAX,[0000]

39. Data Alignment
Data is said to be aligned if all of the bytes to be accessed are located within the same n-byte boundary where n is the maximum number of bytes that can be transferred per memory cycle.
For example the 386 and 486 processors can access 1 byte, 2 bytes, and 4 bytes using BE3-BE0.
Thus, data is said to be aligned if all of the bytes to be accessed are located within the same 4-byte boundary.

40. Data Alignment
Four such address boundaries are possible for 386 and 486 processors as shown in the next figure.
Data items that span across two of these boundaries are said to be misaligned and will require that two bus cycles be performed.

41. Data Alignment
Example 3: Assume a 486 processor executes the instruction MOV EAX, [00005]. Which byte enable signals will be active? How many bus cycles will be required?

42. Data Alignment
Example 3: Assume a 486 processor executes the instruction MOV EAX, [00005]. Which byte enable signals will be active? How many bus cycles will be required?
The double-word (four bytes) at address is to be accessed.
Two bus cycles will be required:
1st bus cycle will be run with BE1-BE3 active and transfer the three bytes at address
2nd bus cycle will be run with only BE0 active. This will transfer the byte at address