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Published byOsborne Marsh Modified over 9 years ago
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Adam Meyer, Michael Beck, Christopher Koch, and Patrick Gerber
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LGA 1155 Socket DMI ◦ 5 GT/s 32 nm manufacturing process 3.4 GHz system clock
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Memory Controller ◦ Inside package Increases performance L1 ◦ Contained in the core L2(mid level cache MLC) ◦ Intermediate L3 ◦ Shared between all cores
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Intel Smart Cache: Demo
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L1 Cache ◦ 64 KB (32 data, 32 instruction) ◦ Has 4 of these caches, one for each core L2 Cache ◦ 256 KB ◦ Has 4 of these caches, one for each core L3 Cache ◦ 8 MB ◦ Shared
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L1 ◦ 4 cycles L2 ◦ 11 cycles L3 ◦ 25 cycles RAM ◦ Approx. 107 cycles
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Integrated Memory Controller (IMC) ◦ Reduces latency Hyperthreading (HT) ◦ Allows one core to appear as two
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Static RAM ◦ Data available until power loss ◦ Idle: 97.5 Watts ◦ Running: 164.7 Watts
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Word Size ◦ 64 Bits Floating Bit Register ◦ 80 Bits Vector Register ◦ 128 Bits
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Address Bus ◦ 32 Bits ◦ 32 GB Max Instruction Set ◦ SSE 4.1/4.2 AVX instruction set ◦ 64 Bits Data Bus ◦ 64 Bits
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Price/Performance ◦ $319.99 (with heatsink and fan) Speed ◦ 5 GT/s ◦ 3.4 GHz Cache Sizes
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CPU World. (2012). Intel Core i7-2600K. Retrieved April 8, 2012, from CPU World: http://www.cpu-world.com/CPUs/Core_i7/Intel-Core%20i7- 2600K%20CM8062300833908.html Gasior, G. (2012). Exploring the impact of memory speed on Core i7 performance. Retrieved April 8, 2012, from The Tech Report: http://techreport.com/articles.x/15967 Intel. (2012). Intel Smart Cache: Demo. Retrieved April 8, 2012, from Intel.com: http://www.intel.com/content/www/us/en/architecture-and- technology/intel-smart-cache.html PC Perspective. (2012). Sandy Bridge-E Processor Review. Retrieved April 8, 2012, from PC Perspective: http://www.pcper.com/reviews/Processors/Intel-Core-i7-3930K- Sandy-Bridge-E-Processor-Review/Power-Consumption-and-Perform Vertrees, R., Coelho, R. O., & Torres, G. (2012). All Core i7 Models. Retrieved April 8, 2012, from Hardware Secrets: http://www.hardwaresecrets.com/article/All-Core-i7-Models/708
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