1. Semiconductor Processing (front-end) Stuart Muter 617.371.3853 smuter@ahh.com 12/02/2002

2. 2 Semiconductor Processing Agenda: An overview of the key steps in semi- conductor processing (how to make one of Stuart’s wafers). A lot of information is in the packet, we will not be able to cover it all.

3. 3 Section AIntroduction to Semiconductor Manufacturing Section BKey Processing Steps - Deposition - Etch - Lithography - Doping and Anneal - CMP Section CFuture Trends Table of Contents

4. SECTION A: Introduction to Semiconductor Manufacturing

5. 5 Deposition - CVD - PVD - Oxidation Etch Lithography Doping and Anneal - Diffusion - Ion Implant - RTP CMP Front End Processing Key Steps

6. 6 Moore’s Law Source: www.intel.com Wafer Sizes Source: Design News Transistor density doubles every 2 years

7. 7 IC Feature Size Trends

8. 8 0.13 micron critical dimension (human hair diameter is approx. 100 microns). 7 metal layers 25 mask steps 300 - 400 process steps State of the Art Semi Device

9. 9 300mm wafers $2-3 billion cost wafer cycle time: 30 -80 days WIP: 20 - 40K wafers Full material automation Cleanroom: Class 10 or 100 Mini-environment: Class 0.1 State of the Art Fab

10. 10 Market Segmentation Semi and Semi-Equipment Industries Worldwide Semiconductor Market Source: WSTS 11/01

11. 11 Wafer Fab Equipment Spending Semi-Equipment Industries WFE Revenue Forecast by Equipment Segment ($ Millions) Source: Gartner Dataquest (July 2002)

12. 12 Device Manufacturing Fab0.5µ CMOS Process Flow

13. 13 Integrated Circuit Manufacturing Process The “big picture” process

14. SECTION B: Key Processing Steps

15. 15 Typically PVD or MCVD Blanket Metal Deposition

16. 16 Preferred conductor deposition technology Barrier and seed layer for Cu DC/RF magnetron sputtering Conductors: - Al (interconnect), Ti, TiN, TiW (barrier and ARC), W (vias), Cu Physical Vapor Deposition