1. A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX-77840

2. Outline Introduction Introduction Previous Work Previous Work Objective Objective Approach Approach Cross-bar Bandwidth (CBB) Cross-bar Bandwidth (CBB) Power-adjusted CBB Power-adjusted CBB Experimental Results Experimental Results Conclusions Conclusions

3. Introduction New fabrication process development New fabrication process development Width Width Spacing Spacing Height Height Inter-layer heights Inter-layer heights Traditionally, fabrication team determines Traditionally, fabrication team determines these values, and design team uses the values This may lead to sub-optimal design This may lead to sub-optimal design

4. Introduction Minimum dimension wires lead to increased scale of integration. However… Minimum dimension wires lead to increased scale of integration. However… This leads to a large number of wires This leads to a large number of wires Inter-wire parasitic capacitance may increase Inter-wire parasitic capacitance may increase Overall circuit speed may decrease Overall circuit speed may decrease Increasing inter-layer dielectric heights Increasing inter-layer dielectric heights Reduces capacitance between wires Reduces capacitance between wires Increases via resistance and reduces via reliability Increases via resistance and reduces via reliability Recently, wire delay dominates the logic delay Recently, wire delay dominates the logic delay Hence the problem of interconnect sizing is important Hence the problem of interconnect sizing is important

5. Introduction Design team would provide several sets of acceptable wiring dimensions Design team would provide several sets of acceptable wiring dimensions Fabrication team selects the set which maximizes both yield and manufacturability Fabrication team selects the set which maximizes both yield and manufacturability This process may be iterated. This process may be iterated. Designers need some metrics to come up with the sets of wiring dimensions Designers need some metrics to come up with the sets of wiring dimensions We propose two metrics to guide the process of selecting wiring dimensions We propose two metrics to guide the process of selecting wiring dimensions

6. Previous Work Analytical Methods Analytical Methods Simplifying assumptions need to be made Simplifying assumptions need to be made Deodhar et. al. assume that grounding wires on present on either side of an interconnect Deodhar et. al. assume that grounding wires on present on either side of an interconnect Davis et. al. considered stochastic interconnect distribution to compute interconnect sizing which minimizes power consumption Davis et. al. considered stochastic interconnect distribution to compute interconnect sizing which minimizes power consumption Li et. al. proposed metrics only for global interconnect optimization Li et. al. proposed metrics only for global interconnect optimization Only wire width and spacing are considered Only wire width and spacing are considered

7. Objective Optimal wiring configuration depends upon several non-linear parameters Optimal wiring configuration depends upon several non-linear parameters A closed form model is not feasible A closed form model is not feasible Want to develop metrics that model delay and power of any interconnect configuration Want to develop metrics that model delay and power of any interconnect configuration Cross-bar bandwidth (CBB) Cross-bar bandwidth (CBB) Power-adjusted cross-bar bandwidth (PCBB) Power-adjusted cross-bar bandwidth (PCBB) Should be applicable to any interconnect layer Should be applicable to any interconnect layer

8. Approach - overview Define two metrics -- CBB and PCBB Define two metrics -- CBB and PCBB Extract resistance and capacitance for various wiring configurations Extract resistance and capacitance for various wiring configurations Evaluate CBB and PCBB for different wiring configurations Evaluate CBB and PCBB for different wiring configurations Vary wire height, width, spacing and inter-layer dielectric in a feasible range Vary wire height, width, spacing and inter-layer dielectric in a feasible range Select the optimal wiring configuration empirically Select the optimal wiring configuration empirically

9. Approach Cross-bar bandwidth Cross-bar bandwidth Bandwidth of a wire times the number of wires in an average size rectangle Bandwidth of a wire times the number of wires in an average size rectangle Higher CBB value implies higher maximum data transfer rate Higher CBB value implies higher maximum data transfer rate Power-adjusted CBB Power-adjusted CBB Weighted sum of CBB and power consumption of interconnects in a rectangular area Weighted sum of CBB and power consumption of interconnects in a rectangular area We perform sizing of METAL1 through METAL4 conductors We perform sizing of METAL1 through METAL4 conductors However, this approach can be used for any metal layer However, this approach can be used for any metal layer

10. Approach Interconnect dimensions used in our study Interconnect dimensions used in our study

11. Approach Wiring configuration for METAL1 and METAL2 Wiring configuration for METAL1 and METAL2 Similar configuration is used for METAL3 and METAL4 Similar configuration is used for METAL3 and METAL4

12. Approach To evaluate CBB or PCBB for any metal layer i, we need their average length l i To evaluate CBB or PCBB for any metal layer i, we need their average length l i Placed and routed several MCNC circuits Placed and routed several MCNC circuits Average length l i Average length l i

13. Cross-bar Bandwidth Consider a rectangle of size l 1 by l 2 Consider a rectangle of size l 1 by l 2 Via resistance: Via resistance: Elmore delay Elmore delay where: c 1 & c 2 are extracted per unit length capacitances where: c 1 & c 2 are extracted per unit length capacitances CBB CBB

14. Power-adjusted CBB Charging current Charging current Assume Assume Total power consumption Total power consumption PCBB PCBB

15. CBB & PCBB with R driver Including driver resistance R driver Including driver resistance R driver Elmore delay Elmore delay CBB with driver included CBB with driver included PCBB with driver included PCBB with driver included

16. Experimental Results Extracted wire capacitances for 70nm process using SPACE 3D-capacitance extractor Extracted wire capacitances for 70nm process using SPACE 3D-capacitance extractor Computed CBB and PCBB (for  = 0.4) for several wiring configurations Computed CBB and PCBB (for  = 0.4) for several wiring configurations METAL1 and METAL2 Parameters METAL3 and METAL4 Parameters

17. METAL1 & METAL2 - CBB CBB for all parameter variation CBB for all parameter variation Order of variation: Order of variation: w 12 w 12 s 12 s 12 L 2 L 2 L 1 L 1 h 12 h 12 L 1 has no effect on CBB therefore, select its lowest value i.e. 200nm

18. METAL1 & METAL2 - CBB Varying: Varying: w 12 w 12 s 12 s 12 L 2 L 2For L 1 =200nm Optimal Values w 12 = 140nm s 12 = 100nm CBB is maximum for w 12 = 140nm CBB is maximum for s 12 = 100nm

19. METAL1 & METAL2 - CBB Vary h 12 for optimal values of w 12, s 12 and L 1 Vary h 12 for optimal values of w 12, s 12 and L 1 and a fixed value of L 2 and a fixed value of L 2 CBB is maximum for h 12 = 300nm

20. METAL1 & METAL2 - CBB Vary L 2 for optimal values of w 12, s 12, L 1 and h 12 Vary L 2 for optimal values of w 12, s 12, L 1 and h 12 Optimal value of Optimal value of L 2 is 200nm L 2 is 200nm CBB is maximized for smallest value of L 2

21. METAL1 & METAL2 - PCBB For  = 0.4 For  = 0.4 PCBB is maximum w 12 140nm s 12 140nm L1L1L1L1200nm L2L2L2L2200nm h 12 240nm

22. Optimal Sizing For METAL1 and METAL2 For METAL1 and METAL2 For METAL3 and METAL4 For METAL3 and METAL4

23. CBB and PCBB Improvement For METAL1 and METAL2 optimal sizing yield For METAL1 and METAL2 optimal sizing yield 12.94% increase in CBB 12.94% increase in CBB 19.29% in PCBB 19.29% in PCBB METAL3 and METAL4 METAL3 and METAL4 16.5% increase in CBB 16.5% increase in CBB 17.15% increase in PCBB 17.15% increase in PCBB

24. Optimal Sizing For METAL1 and METAL2 with driver resistance For METAL1 and METAL2 with driver resistance For METAL3 and METAL4 with driver resistance For METAL3 and METAL4 with driver resistance

25. CBB and PCBB Improvement For METAL1 and METAL2 with driver resistance For METAL1 and METAL2 with driver resistance For METAL3 and METAL4 with driver resistance For METAL3 and METAL4 with driver resistance For 300 ohm drivers, the improvements are 31.7% and 68.9% (CBB driver and PCBB driver respectively) For 300 ohm drivers, the improvements are 31.7% and 68.9% (CBB driver and PCBB driver respectively) Improvements for other resistance values are similar, and reported in the paper. Improvements for other resistance values are similar, and reported in the paper.

26. Conclusions Optimal wiring configuration depends upon several parameters therefore, closed form model is not feasible Optimal wiring configuration depends upon several parameters therefore, closed form model is not feasible We proposed 2 metrics for wire sizing i.e. CBB and PCBB which account for delay and power We proposed 2 metrics for wire sizing i.e. CBB and PCBB which account for delay and power Without considering driver resistance, our approach yields up to 16% improvement in CBB and 19% improvement in PCBB Without considering driver resistance, our approach yields up to 16% improvement in CBB and 19% improvement in PCBB With driver resistance, the percent improvement is even higher With driver resistance, the percent improvement is even higher

27. Thank You!