1. Computer Architecture 2- 0 2. Instruction: Language of the Computer 2.1 Introduction 2.2 Operations of the Computer Hardware 2.3 Operands of the Computer Hardware 2.4 Representing Instructions in the Computer 2.5 Logical Operations 2.6 Instructions for Making Decisions 2.7 Supporting Procedures in Computer Hardware 2.8 Communicating with People 2.9 MIPS Addressing for 32-Bit Immediates and Addresses 2.10 Translating and Starting a Program 2.11 How Compilers Optimize 2.12 How Compilers Work: An Introduction 2.13 A C Sort Example to Put It All Together 2.14 Implementing an Object-Oriented Language 2.15 Arrays versus Pointers 2.16 Real Stuff: IA-32 Instructions 2.17 Fallacies and Pitfalls 2.18 Concluding Remarks 2.19 Historical Perspective and Further Reading 2.20 Exercises

2. Computer Architecture 2- 1 2.1 Introduction  Instructions  The words of a machine's language  Instruction set  The vocabulary of the language  RISC vs. CISC  Reduced Instruction Set Computer  Complex Instruction Set Computer Back to chapter overview

3. Computer Architecture 2- 2 Common Goal of the Computer Designers  To find a language that makes it easy to build the hardware and the compiler, while maximizing performance and minimizing cost.  “Simplicity of the equipment”  MIPS  Microprocessor without Interlocked Pipeline Stages  Typical of instruction set designed since the 1980s  Produced almost 100 millions in 2002  Used by ATI Technologies, Broadcom, Cisco, NEC, Nintendo, Silicon Graphics, Sony, Texas Instruments, Toshiba, and etc.

4. Computer Architecture 2- 3 2.2 Operations of the Computer Hardware  MIPS arithmetic instructions  add a,b,c # a = b + c  sub a,b,c # a = b - c  Design Principle 1 : Simplicity favors regularity.  Always three operands  Keeping the hardware simple  Example: f=(g+h)-(i+j); add t0,g,h # t0 = g + h add t1,i,j# t1 = i + j sub f,t0,t1# f = to - t1 = (g+h)-(i+j) Back to chapter overview

5. Computer Architecture 2- 4 2.3 Operands of the Computer Hardware  Arithmetic instruction’s operands must be registers  Only 32 registers provided  Compiler associates variables with registers  What about programs with lots of variables What about programs with lots of variables ProcessorI/O Control Datapath Memory Input Output Back to chapter overview

6. Computer Architecture 2- 5 MIPS registers: Fig 2.18Fig 2.18  32 registers  Variables: $s0, $s1, $s2, … $s7  Temporary registers: $t0, $t1, $t2, … $t9  Design Principle 2 : Smaller is faster.  A very large number of registers  Convenient for the programmers  But, longer distance to travel for the electronic signals  Increased clock cycle time

7. Computer Architecture 2- 6 Example: f=(g+h)-(i+j);  f, g, h, i, j -> $s0, $s1, $s2, $s3, $s4 [Answer] add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1

8. Computer Architecture 2- 7 Memory Operands  Arrays and structures  Too many data elements  Stored in memory, not in registers  Data transfer instructions  load: lw (load word) in MIPS  store: sw (store word) in MIPS  Example: g = h + A[8]; base address of A -> $s3 [Answer] lw $t0, 8($s3) # $t0 gets A[8] add $s1, $s2, $t0 # g = h + A[8]

9. Computer Architecture 2- 8 Actual MIPS Memory Structure Figure 2.3

10. Computer Architecture 2- 9 Hardware Software Interface  Byte addressing  Alignment restriction  Big endian vs. little endian  Little endian  Using the address of the rightmost (or “little end”) byte as the word address  Intel IA-32, DEC PDP 11, VAX-11  Big endian  Using the address of the leftmost (or “big end”) byte as the word address  MIPS, IBM S/360 and S/370, Motorola 680x0

11. Computer Architecture 2- 10 Example: A[12] = h + A[8];  base address of A -> $s3  h -> $s2 [Answer] lw $t0,32($s3) # Temporary reg. $t0 gets A[8] add $t0,$s2,$t0 # Temporary reg. $t0 gets h+A[8] sw $t0,48($s3) # Stores h+A[8] back into A[12] Hardware Software Interface  Register spilling

12. Computer Architecture 2- 11 Constant or Immediate Operands  Constant operands  More than half of the SPEC2000 operands  Adding 4 to $s3 without constant operand lw $t0,AddrConstant4($s1) # $t0=constant 4 add $s3,$s3,$t0 # $s3=$s3+$t0 ($t0=4)  Faster version addi(add immediate) instruction addi $s3,$s3,4 # $s3=$s3+4  Design Principle 3 : Make the common case fast.  Constant operands are frequently used.  Arithmetic operations with constant operands.

13. Computer Architecture 2- 12 2.4 Representing Instructions in the Computer  Example : machine instruction add $t0, $s1, $s2 [Answer] 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits  First and last fields: addition operation  Second field: register number of the first source operand ($s1)  Third field: register number of the other source operand ($s2)  Fourth field: number of the destination register ($t0)  Fifth field: unused in this instruction (set to 0) Back to chapter overview

14. Computer Architecture 2- 13 MIPS Fields 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits  op: Basic operation of the instruction (opcode)  rs: The first register source operand  rt: The second register source operand  rd: The register destination operand It gets the result of the operation.  shamt: Shift amount (Explained in §2.5)§2.5  funct (function): This field selects the specific variant of the operation in the op field, and is sometimes called the function code. (cf) opcode extension  R-type (Register-type)

15. Computer Architecture 2- 14 I-type Instruction Format  Design Principle 4 : Good design demands good compromises. [Example] MIPS instructions  Same length but different formats  I-type (Immediate-type) 6 bits 5 bits 5 bits 16 bits

16. Computer Architecture 2- 15 Example: A[300]=h+A[300]; lw $t0,1200($t1)# Temporary reg. $t0 gets A[300] add $t0,$s2,$t0# Temporary reg. $t0 gets h+A[300] sw $t0,1200($t1)# Stores h+A[300] back into A[300] [Answer]

17. Computer Architecture 2- 16 The Big Picture  Instructions are represented as numbers.  Programs can be stored in memory to be read or written, just like numbers. Figure 2.8 Stored-program concept

18. Computer Architecture 2- 17 2.5 Logical Operations Fig. 2.9 Logical operators Back to chapter overview OperationsCJavaMIPS Shift left << sll Shift right >> srl Bit-by-bit AND &&and, andi Bit-by-bit OR ||or, ori Bit-by-bit NOT ~~nor

19. Computer Architecture 2- 18 MIPS Shift Instructions  sll (shift left logical)  srl (shift right logical)  Instruction format  sll $t2, $s0, 4 # reg $t2 = reg $s0 << 4 bits op rs rt rd shamt funct 00161040

20. Computer Architecture 2- 19 Logical Instructions  and $t0,$t1,$t2 # reg $t0 = reg $t1 & reg $t2  or $t0,$t1,$t2 # reg $t0 = reg $t1 | reg $t2  nor $t0,$t1,$t2 # reg $t0 = ~(reg $t1 | reg $t2)  andi $s1,$s1,100 # reg $s1 = reg $s1 & 100  ori $s1,$s1,100 # reg $s1 = reg $s1 | 100

21. Computer Architecture 2- 20 2.6 Instructions for Making Decisions  Similar to an if statement with a go to statement  beq register1, register2, L1  bne register1, register2, L1  Example if (i==j) f=g+h; else f=g-h; [Answer] bne $s3,$s4,Else# go to Else if i≠j add $s0,$s1,$s2 # f=g+h (skipped if i≠j) j Exit# go to Exit Else: sub $s0,$s1,$s2 # f=g-h (skipped if i=j) Exit: Back to chapter overview

22. Computer Architecture 2- 21 Loops  Example while (save[i]==k) i += 1; [Answer] Loop: sll $t1,$s3,2 # Temp reg $t1 = 4*i add $t1,$t1,$s6 # $t1 = address of save[i] lw $t0,0($t1) # Temp reg $t0 = save[i] bne $t0,$s5,Exit # go to Exit if save[i]≠k addi $s3,$s3,1 # i = i + 1 ( 원서 error) j Loop # go to Loop Exit:

23. Computer Architecture 2- 22 slt(set on less than) Instruction  slt $t0,$s3,$s4# if($s3<$s4) then $t0=1 # else $t0=0  slti $t0,$s2,10# $t0=1 if $s2<10  Pseudo instruction blt $s0,$s1,Less # branch on less than  Why no blt instruction in MIPS architecture?  It would stretch the clock cycle time, or it would take extra clock cycles per instruction.  Hardware/Software Interface  All comparisons are possible with slt, beq, bne with $zero.

24. Computer Architecture 2- 23 Case/Switch Statement  Jump address table  A table of addresses of alternative instruction sequences  jr (jump register) instruction jr $t0# jump to the address specified # in a register($t0)  Implementing case/switch 1. Loading the appropriate entry from the jump table in a register 2. Jumping to the proper address using a jump register

25. Computer Architecture 2- 24 2.7 Supporting Procedures in Computer Hardware  Registers  $a0 - $a3 : 4 argument register in which to pass parameters  $v0 - $v1 : 2 value registers in which to return values  $ra : 1 return address register to return to the point of origin  jal (jump-and-link) instruction jal ProcedureAddress # $ra ← PC + 4, # PC ← ProcedureAddress  Return from procedure jr $ra Back to chapter overview

26. Computer Architecture 2- 25 Using More Registers  Spilling registers  More than 4 arguments  More than 2 return values  Stack  Ideal data structure for spilling registers  Stack Pointer $sp (=$29)

27. Computer Architecture 2- 26 Example : Leaf Procedure int leaf_example (int g, int h, int i, int j) { int f; f = (g + h) - (i + j); return f; } [Answer] $a0 = g, $a1 =h, $a2 = i, $a3 = j, $s0 = f leaf_example: addi $sp,$sp,-12 # adjust stack to make room for 3 items sw $t1,8($sp) # save register $t1 for use afterwards sw $t0,4($sp) # save register $t0 for use afterwards sw $s0,0($sp) # save register $s0 for use afterwards

28. Computer Architecture 2- 27 [Answer] - continued add $t0,$a0,$a1 # register $t0 contains g+h add $t1,$a2,$a3 # register $t1 contains i+j sub $s0,$t0,$t1 # f=$t0-$t1, which is (g+h)-(i+j) add $v0,$s0,$zero # returns f ($v0=$s0+0) lw $s0,0($sp) # restore register $s0 for caller lw $t0,4($sp) # restore register $t0 for caller lw $t1,8($sp) # restore register $t1 for caller add $sp,$sp,12 # adjust stack to delete 3 items jr $ra # jump back to calling routine

29. Computer Architecture 2- 28 Register Preservation  $t0 - $t9 : not preserved  $s0 - $s7 : preserved  What is and what is not preserved across a procedure call: Fig 2.15

30. Computer Architecture 2- 29 MIPS Register Convention Name Register Number Usage $zero 0the constant value 0 $at 1reserved for assembler $v0-$v1 2-3values for results and expression evaluation $a0-$a3 4-7arguments $t0-$t9 8-15,24-25temporaries $s0-$s7 16-23saved $k0-$k1 26-27reserved for operating system $gp 28global pointer $sp 29stack pointer $fp 30frame pointer $ra 31return address Figure 2.18

31. Computer Architecture 2- 30 2.8 Communicating with People  Character code  ASCII (American Standard Code for Information Interchange)  Unicode  Load byte instructions  lb $t0,0($sp)  Loading a byte from memory and placing it in the rightmost 8 bits of a register  Store byte instructions  sb $t0,0($gp)  Taking a byte from the rightmost 8 bits of a register and writing it to memory Back to chapter overview

32. Computer Architecture 2- 31 Example void strcpy (char x[ ], char y[ ]) { int i; i = 0; while ((x[i] = y[i]) != ‘\0’) /* copy & test byte */ i += 1; }

33. Computer Architecture 2- 32 [Answer] strcpy: addi $sp,$sp,-4 # adjust stack for 1 more item sw $s0,0($sp) # save $s0 add $s0,$zero,$zero # i=0+0 L1: add $t1,$s0,$a1 # address of y[i] in $t1 lb $t2,0($t1) # $t2=y[i] add $t3,$s0,$a0 # address of x[i] in $t3 sb $t2,0($t3) # x[i]=y[i] beq $t2,$zero,L2 # if y[i]==0, go to L2 addi $s0,$s0,1 # i=i+1 j L1 # go to L1 L2: lw $s0,0($sp) # y[i]==0: end of string; # restore old $s0 addi $sp,$sp,4 # pop 1 word off stack jr $ra # return

34. Computer Architecture 2- 33 Characters and Strings in Java  Unicode  Used by Java  16 bits for a character  UTF-8, UTF-16 and UTF-32  Halfword transfer instructions lh $t0,0($sp) # Read 16 bits from source sh $t0,0($gp) # Write 16 bits to destination  Strings in Java  Standard class  Special built-in support and predefined methods for concatenation, comparison and conversion.  Including a word that gives the length of the string.

35. Computer Architecture 2- 34 2.9 MIPS Addressing for 32-Bit Immediates and Addresses 32-Bit Immediate Operands  Load upper immediate(lui) Instruction lui $t0,255 $t0  Example $s0 <= 0000 0000 0011 1101 0000 1001 0000 0000 [Answer] lui $s0,61 # 61 10 = 0000 0000 0011 1101 2 ori $s0,$s0,2304 # 2304 10 = 0000 1001 0000 0000 2 Back to chapter overview

36. Computer Architecture 2- 35 Addressing in Branches and Jumps  J-type instruction format 6 bits 26 bits  Direct addressing mode Direct addressing mode  Addressing in jump instruction  j 10000# branch address = 10000  Word address  Branch address = 10000 * 4  j 10000# branch address = 40000

37. Computer Architecture 2- 36 Branch Address  Pseudo-direct addressing  Upper 4 bits of PC are unchanged.  Address boundary of 256 MB  Jump address 4 bits 26 bits 2 bits  PC-relative addressing mode PC-relative addressing mode  Branch target address = (PC+4) + Branch offset  New PC = (PC+4) ± 2 15 word 6 bits 5 bits 5 bits 16 bits from PCfrom instruction00

38. Computer Architecture 2- 37 Example: Showing Branch Offset Loop: sll $t1,$s3,2 # Temp reg $t1 = 4*i add $t1,$t1,$s6 # $t1 = address of save[i] lw $t0,0($t1) # Temp reg $t0 = save[i] bne $t0,$s5,Exit # go to exit if save[i]≠k addi $s3,$s3,1 # i = i+1 j Loop # go to Loop Exit:

39. Computer Architecture 2- 38 Example: Branching Far Away  beq $s0,$s1,L1 But L1 is too far. [Answer] bne $s0,$s1,L2 j L1 L2 :

40. Computer Architecture 2- 39 MIPS Addressing Modes Figure 2.24

41. Summary  InstructionMeaning add $s1,$s2,$s3$s1 = $s2 + $s3 sub $s1,$s2,$s3$s1 = $s2 – $s3 lw $s1,100($s2)$s1 = Memory[$s2+100] sw $s1,100($s2)Memory[$s2+100] = $s1 bne $s4,$s5,LNext instr. is at Label if $s4≠$s5 beq $s4,$s5,LNext instr. is at Label if $s4=$s5 j LabelNext instr. is at Label  Formats: op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address RIJRIJ

42. Computer Architecture 2- 41 To summarize:

43. Computer Architecture 2- 42 Decoding Machine Language  Example 00af8020 hex [Answer] 0000 0000 1010 1111 1000 0000 0010 0000 Opcode=000000 -> R-type 00000000101011111000000000100000 op rs rt rd shamt funct Funct = 100000 -> add (See Fig. 2.25) $5 = $a1, $15 = $t7, $16 = $s0 (See Fig. 2.18)Fig. 2.18 add $s0,$a1,$t7

44. Computer Architecture 2- 43 2.10 Translating and Starting a Program Figure 2.28 Back to chapter overview

45. Computer Architecture 2- 44 2.11 How Compilers Optimize Figure 2.31 Back to chapter overview

46. Computer Architecture 2- 45 2.18 Concluding Remarks  4 principles for the designers of instruction sets 1. Simplicity favors regularity. 2. Smaller is faster. 3. Make the common case fast. 4. Good design demands good compromises. Back to chapter overview

47. Computer Architecture 2- 46 Instruction Categories Instruction class MIPS example Frequency IntegerFl. Pt. Arithmetic add,sub,addi 24%48% Data transfer lw,sw,lb,sb,lui 36%39% Logical and,or,nor,andi, ori,sll,srl 18% 4% Conditional branch beq,bne,slt,slti 18% 6% Jump j,jr,jal 3% 0% Figure 2.48

48. Computer Architecture 2- 47 MIPS Instructions Figure 2.47

49. Computer Architecture 2- 48 2.19 Historical Perspective and Further Reading Accumulator Architectures  Single accumulator  EDSAC, IBM 701, PDP-8  Extended accumulator = dedicated register = special-purpose register  Intel 8086 Back to chapter overview

50. Computer Architecture 2- 49 General-Purpose Register Architectures  Register-memory architecture  IBM 360, PDP-11, Motorola 68000  Load-store or register-register architecture  CDC 6600, MIPS, SPARC  Memory-memory architecture  VAX ?

51. Computer Architecture 2- 50 Number of General-Purpose Registers Figure 2.19.1

52. Computer Architecture 2- 51 Compact Code and Stack Architectures  Instruction length  MIPS R2000, SPARC are RISC architectures … 4 bytes  Intel IA-32 … 1 ∼ 17 bytes  IBM S/360 … 2, 4, 6 bytes  VAX … 1 ∼ 54 bytes  Stack computers  Radical approach in the 1960s  In the belief that it was too hard for compilers to utilize registers effectively  Abandoned registers  HP3000, B5500  Java bytecode  Compact instruction encoding is desirable.

53. Computer Architecture 2- 52 High-Level-Language Computer Architectures  Goal  Making the hardware more like the programming language  More efficient programming languages and compilers, plus expanding memory  Commercially failed  Burroughs B5000

54. Computer Architecture 2- 53 RISC  Reduced Instruction Set Computer  Design philosophies  Fixed instruction lengths  Load-store instruction set  Limited addressing modes  Limited operations  ARM, Hitachi SH, MIPS R2000/R3000/R4000/R10000, IBM PowerPC, DEC Alpha, Sun Sparc/SuperSparc/UltraSparc, Hewlett Packard PA-RISC, Intel i860/i960, Motorola 88100/88110, AMD 29000