1. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 1 Introduction to Electronic Circuit Design Richard R. Spencer Mohammed S. Ghausi

2. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 2 Figure 7-1 How to model independent sources for DC analysis. (a) A voltage source. (b) A current source.

3. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 3 Figure 7-2 The simplest possible DC and large-signal low- frequency models for (a) a resistor, (b) an inductor, and (c) a capacitor.

4. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 4 Figure 7-3 A plot of (7.1) for a diode with I S = 10 -14 A and n = 1 and a piecewise-linear approximation to the characteristic. (b) The corresponding circuit model when the diode is forward biased. (A pn-junction diode symbol is used for illustration, but the same form of model applies for Schottky diodes.)

5. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 5 Figure 7-12 The large-signal low-frequency models used for a diode; (a) forward- biased, (b) reverse-biased, and (c) in breakdown.

6. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 6 Figure 7-15 The collector characteristics of a BJT, showing the forward-active, cutoff, and saturation regions of operation.

7. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 7 Figure 7-17 Large-signal low-frequency models for an npn BJT in forward-active operation: (a) the common-emitter model and (b) the common-base model. Figure 7-24 The large-signal model for an npn transistor in saturation. Figure 7-25 Models for an npn transistor with (a) the base- emitter junction broken down and (b) the base-collector junction broken down.

8. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 8 Figure 7-28 The large-signal low-frequency models for a pnp BJT in (a) forward-active operation in a common-emitter connection, (b) forward-active operation in a common-base connection, (a) cutoff, and (d) saturation.

9. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 9 Figure 7-30 MOSFET drain characteristics, showing forward-active operation (i.e., saturation), the linear region, and cutoff.

10. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 10 Figure 7-31 A large-signal low-frequency model for an n- channel MOSFET in saturation. Figure 7-36 The large-signal low-frequency model for a MOSFET in the linear region of operation. The resistance is given by (7.18) for small V DS. Figure 7-37 The low-frequency model for a MOSFET when cut off. Figure 7-41 The model for a MOSFET when the drain-to- source breakdown voltage (BV DS ) has been reached.

11. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 11 Figure 7-42 Large-signal low-frequency models for a p-channel MOSFET in (a) saturation, (b) cutoff, and (c) the linear region.

12. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 12 Figure 7-44 A large-signal low-frequency model for a p-channel JFET in saturation. Figure 7-43 A large-signal low-frequency model for a n-channel JFET in saturation.

13. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 13 Figure 7-46 The most common single-transistor discrete BJT biasing circuit.

14. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 14 Figure A7-1 A large-signal DC model of a BJT biasing circuit. (b) A circuit that yields the same loop equation as (a), but with the current equal to I B everywhere in the loop. (c) A circuit that yields the same loop equation as (a), but with the current equal to I E everywhere in the loop.

15. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 15 Figure 7-49 A discrete biasing circuit for FET amplifiers (shown with an n-channel enhancement- mode MOSFET).

16. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 16 Figure 7-50 The large-signal DC equivalent for the circuit in Figure 7-49

17. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 17 Figure 7-60 A transistor current source.

18. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 18 Figure 7-62 A bipolar current mirror.

19. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 19 Figure 7-65 A multiple-output current mirror.

20. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 20 Figure 7-67 A Widlar current source.

21. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 21 Figure 7-68 A MOSFET current mirror.

22. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 22 Figure 7-69 A multiple output current mirror.

23. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 23 Figure 7-70 A differential amplifier.

24. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 24 Figure A7-2 A p-type generic transistor: (a) the schematic symbol and (b) a model.

25. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 7, slide 25 Figure 7-71 An actively loaded differential pair.