1. BJT Fixed Bias ENGI 242 ELEC 222

2. January 2004ENGI 242/ELEC 2222 BJT Biasing 1 For Fixed Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point –Graphical Solution using Loadlines –Computational Analysis Design and test design using a computer simulation

3. January 2004ENGI 242/ELEC 2223 Complete CE Amplifier with Fixed Bias

4. January 2004ENGI 242/ELEC 2224 Fixed Bias and Equivalent DC Circuit

5. January 2004ENGI 242/ELEC 2225 Fixed-Bias Circuit

6. January 2004ENGI 242/ELEC 2226 DC Equivalent Circuit

7. January 2004ENGI 242/ELEC 2227 Base-Emitter (Input) Loop Using Kirchoff’s voltage law: – V CC + I B R B + V BE = 0 Solving for I B :

8. January 2004ENGI 242/ELEC 2228 Collector-Emitter (Output) Loop Since: I C =  I B Using Kirchoff’s voltage law: – V CC + I C R C + V CE = 0 Because: V CE = V C – V E Since V E = 0V, then: V C = V CE And V CE = V CC - I C R C Also: V BE = V B - V E with V E = 0V, then: V B = V BE

9. January 2004ENGI 242/ELEC 2229 BJT Saturation Regions When the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that:

10. January 2004ENGI 242/ELEC 22210 Determining I csat

11. January 2004ENGI 242/ELEC 22211 Determining I CSAT for the fixed-bias configuration

12. January 2004ENGI 242/ELEC 22212 Load Line Analysis

13. January 2004ENGI 242/ELEC 22213 Load Line Analysis The end points of the line are : I Csat and V CE cutoff For load line analysis, use V CE = 0 for I CSAT, and I C = 0 for V CEcutoff I Csat : V CEcutoff : Where I B intersects with the load line we have the Q point Q-point is the particular operating point: Value of R B Sets the value of I B Where I B and Load Line intersect Sets the values of V CE and I C.

14. January 2004ENGI 242/ELEC 22214 Circuit values effect Q-point

15. January 2004ENGI 242/ELEC 22215 Circuit values effect Q-point (continued )

16. January 2004ENGI 242/ELEC 22216 Circuit values effect Q-point (continued)

17. January 2004ENGI 242/ELEC 22217 Load-line analysis

18. January 2004ENGI 242/ELEC 22218 DC Fixed Bias Circuit Example

19. January 2004ENGI 242/ELEC 22219 Loadline Example Family of Curves

20. Emitter Stabilized Bias ENGI 242 ELEC 222

21. January 2004ENGI 242/ELEC 22221 BJT Emitter Bias For the Emitter Stabilized Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point –Graphical Solution using Loadlines –Computational Analysis Design and test design using a computer simulation

22. January 2004ENGI 242/ELEC 22222 Improved Bias Stability The addition of R E to the Emitter circuit improves the stability of a transistor output Stability refers to a bias circuit in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor forward current gain (  ) The temperature (T A or ambient temperature) surrounding the transistor circuit is not always constant Therefore, the transistor  is not a constant value

23. January 2004ENGI 242/ELEC 22223 Emitter-Stabilized Bias Circuit Adding an emitter resistor to the circuit between the emitter lead and ground stabilizes the bias circuit over Fixed Bias

24. January 2004ENGI 242/ELEC 22224 Base-Emitter Loop

25. January 2004ENGI 242/ELEC 22225 Equivalent Network

26. January 2004ENGI 242/ELEC 22226 Reflected Input impedance of R E

27. January 2004ENGI 242/ELEC 22227 Base-Emitter Loop Applying Kirchoffs voltage law:- V CC + I B R B + V BE +I E R E = 0 Since: I E = (  + 1) I B We can write: - V CC + I B R B + V BE + (  + 1) I B R E = 0 Grouping terms and solving for I B : Or we could solve for I E with:

28. January 2004ENGI 242/ELEC 22228 Collector-Emitter Loop

29. January 2004ENGI 242/ELEC 22229 Collector-Emitter Loop Applying Kirchoff’s voltage law: - V CC + I C R C + V CE + I E R E = 0 Assuming that I E  I C and solving for V CE : V CE = V CC – I C (R C + R E ) If we can not use I E  I C the I C =  I E and:V CE = V CC – I C (R C +  R E ) Solve for V E : V E = I E R E Solve for V C : V C = V CC - I C R C or V C = V CE + I E R E Solve for V B : V B = V CC - I B R B or V B = V BE + I E R E

30. January 2004ENGI 242/ELEC 22230 Transistor Saturation At saturation, V CE is at a minimum We will find the value V CEsat = 0.2V For load line analysis, we use V CE = 0 To solve for I CSAT, use the output KVL equation:

31. January 2004ENGI 242/ELEC 22231 Load Line Analysis The load line end points can be calculated: At cutoff: At saturation:

32. January 2004ENGI 242/ELEC 22232 Emitter Stabilized Bias Circuit Example

33. January 2004ENGI 242/ELEC 22233 Design of an Emitter Bias CE Amplifier Where.1V CC  V E .2V CC And.4V CC  V C .6V CC

34. January 2004ENGI 242/ELEC 22234 Emitter Bias with Dual Supply

35. January 2004ENGI 242/ELEC 22235 Emitter Bias with Dual Supply Input Output