1. CAE tools and technology challenges in making deep sub-micron IC designs Kostas Kloukinas CERN, PH-ESE dept. CH1211, Geneve 23 Switzerland ESE Group seminar 30/3/2010

2. Overview Technology Challenges Modern CAE Tools IC design CAE tools at CERN 30/3/10 Kostas.Kloukinas@cern.ch 2

3. How it all got started…. 30/3/10 Kostas.Kloukinas@cern.ch 3 10 cm process.35 um process

4. …and the story continues… 30/3/10 Kostas.Kloukinas@cern.ch 4 CAE Tools co-evolved with process technology

5. What drives CAE tools Innovation CAE Tools Technology Challenges Design Challenges Productivity Requirements 30/3/10 Kostas.Kloukinas@cern.ch 5

6. CAE tools have to coop with: Deep Submicron effects “Black List”  Numerous and Complicated Design Manufacturing Rules  Leakage currents of devices  Interconnect parasitics  Process Variations  Process Fault modes and Design For Manufacturability (DFM) Design Challenges  System On Chips (SOC) and IP Reuse  Low Power Design techniques  Formal Design Methodologies Digital design flows Analog and Mixed Signal flows Hierarchical Implementation flows  Advanced Verification Techniques 30/3/10 Kostas.Kloukinas@cern.ch 6

7. Complicated Design Rules Design Manual page count:  250nm: 170 pages  130nm: 600 pages + numerous application notes Design Rule Check deck files:  250nm: 5,300 lines  130nm: 13,500 lines  90nm: 38,400 lines  65nm: 89,300 lines One single verification tool is not capable any more to detect all DRC violations!  Foundries require design sign-off verification using independently two verification tools from two different vendors. Tools make use of parameterized cells (Pcells) and automated “analog routers” to assist layout work and increase design productivity. 30/3/10 Kostas.Kloukinas@cern.ch 7 Parameterized cell

8. Full Custom IC Assembly Router Features and Benefits  Device, cell, block and top-level chip assembly routing support.  Design constraint and process rule driven  Interactive signal routing  Multi-net/bus routing support  On the fly Design Rule checking  Variable Width and Spacing rules  Automated signal routing  Automated special net shielding Requirements:  Support from foundry PDK with technology specific design rules and constraints. 30/3/10 Kostas.Kloukinas@cern.ch 8 Tool: Cadence Virtuoso Chip Assembly Router to augment design productivity.

9. Leakage currents affecting Power Digital Circuit Power Dissipation  Dynamic Power dissipation Short circuit power Switching power P = C * f * V 2 dd  Static Power due to leakage currents Leakage currents in deep submicron technologies:  Gate tunneling leakage (a)  Sub-threshold leakage (b)  Reversed biased PN junction leakage (c)  Gate Induced Drain Leakage (b) Leakage Power is a significant component of the total power dissipation in 90nm technologies and below. 30/3/10 Kostas.Kloukinas@cern.ch 9

10. Multiple V T standard cell libraries Multiple V T standard cell libraries.  High V T cells for low power  Low V T cells for high performance  Nominal V T cells for general purpose. Logic synthesis  High performance strategy Synthesize with Low V T libraries and then optimize with High and Nominal.  Low power strategy Synthesize with High V T libraries and then optimize with Low and Nominal.  Integrated strategy Synthesize with all libraries concurrently. State-of-the-art synthesis tools, like Synopsys “Design Compiler” or Cadence “RTL Compiler”, support multi V T synthesis. Efficient synthesis is obtained when it is implemented at a cell level (not block level). CAE tools have to deal with:  Multiple libraries of 1,000s of cells  Highly customized design flows. 30/3/10 Kostas.Kloukinas@cern.ch 10

11. Low Power Design (1/6) 30/3/10 Kostas.Kloukinas@cern.ch 11 Multi Voltage Libraries  Different fixed supply voltages depending performance requirements.  Requires standard cell libraries characterized at different supply voltages Level Shifter cells  Each power domain receives the voltage swing it expects. Power Gating  Power down idle blocks to reduce leakage currents.  Requires special power control cells (switches) as well as isolation and state retention cells. Dynamic Voltage and Frequency scaling.  Voltage and frequency dynamically adjusted in response to changing workloads.  Applicable to processors and microcontrollers. CAE tools are required to handle:  Multiple standard cell libraries characterized at different power supply voltages.  Floorplanning and special power rooting.  Multi modes, Multi Voltage of operation. High-Low Level Shifter Low-High Level Shifter Floorplanning with Level Shifters

12. Low Power Design (2/6) Power Switch cells  In a power gating design, sleep transistors are used as switches to shut off power supplies to parts of a design in standby mode  Power Grid floorplanning Better IR drop management & area optimization. Complexity in Physical Synthesis and Power Routing.  Ring Style floorplanning Less complex P&R especially for existing hard IP blocks For large blocks the IR drop in the center can be high. Isolation & State Retention cells  Isolation logic is typically used at the output of a powered-down block to prevent floating, unpowered signals (represented by unknown or X in simulation) from propagating from powered-down blocks.  To speed power-up recovery, state retention power gating flops can be used to retain their state while the power is off. 30/3/10 Kostas.Kloukinas@cern.ch 12 Power grid distribution Ring style distribution

13. Low Power Design (3/6) Control of the substrate voltage  Basic Principle: Increase the back gate voltage to increase V T and thus decrease leakage. Decrease the back gate voltage to decrease VT and thus increase performance at the expense of leakage power consumption. (Difficult & risky approach) Special Tap cells (fill cells)  Back or forward biasing for performance/leakage optimization N-well voltage different from VDD Substrate or P-well (triple well process) voltage different from VSS Bias voltage routed as signal pin or special power net  Correct well/substrate voltages in case of on-chip power gating Well pins connect wells to always-on power supplies Keep wells “alive” when island is power down V NW must connect to always-on power when using “header” power switches. V PW must connect to always-on power when using “footer” power switches. 30/3/10 Kostas.Kloukinas@cern.ch 13

14. Low Power Design (4/6) Clock Gating  Useful when data only loaded infrequently.  No dynamic power when clock is stopped.  Transformation to the 2 nd implementation can be done automatically by the CAE synthesis tool.  Integrated Clock Gating cells (ICG) are special standard cells that ensure a predictable clock gating behavior.  Controlled with tool specific settings.  Can use normal standard cells but timing issues are always a hazard. Clock Gating: Cloning & Decloning  You can even reduce the power some more by moving the clock gating cells to higher levels in the hierarchy and combining them as much as possible. 30/3/10 Kostas.Kloukinas@cern.ch 14

15. Low Power Design (5/6) 30/3/10 Kostas.Kloukinas@cern.ch 15 Operand Isolation (Data Gating)  Holding inputs to combinatorial blocks constant when their outputs are not required.  Reduces power by preventing switching activity Gate level power optimizations  Cell sizing  Buffering  Pin swapping  Factoring Implementation choices for Data Paths  Multipliers  Adders  Bus Encoding  Pipelining Asynchronous Logic Design  Extremely hard work with practically no support from CAE tools!

16. Low Power Design (6/6) Power intend description languages  Universal Power Format (Synopsys)  Common Power Format (Cadence) Power aware simulation Power aware synthesis Power aware verification Power aware implementation Power aware logic equivalence check Power aware sign-off 30/3/10 Kostas.Kloukinas@cern.ch 16

17. Interconnect Parasitics Increased number of metal layers at finer pitch. The wire interconnect dominates timing  Gate delay equals to interconnect delay at 130nm. Metal interconnects have smaller widths, taller heights, shorter intra-layer spacing.  In 350nm, wire to substrate capacitance was dominant.  In 90nm, wire to wire capacitance is dominant. Increased complexity of interconnect parasitic device extraction:  Copper wire distortions caused primarily due to CMP (Chemical Mechanical Polishing) results in irregular trapezoid conductors.  Below 90nm wireline variations require (min/typ/max) extraction. 30/3/10 Kostas.Kloukinas@cern.ch 17

18. Signal Integrity issues Crosstalk in Deep Submicron  Smaller geometries increase coupling  Technologies have gotten faster. Edge rates are much higher, increasing the likelihood of crosstalk and worsen power/ground bounce.  Chips are much more complex, increasing the likelihood of long parallel wires. Crosstalk induced Noise  The aggressor net causes glitching on the victim net.  If the glitches coincide with clock edges then errors occur. Crosstalk induced Delay  Causing signal to speed up or slow down. CAE Tools involved:  Interconnect parasitic extraction engines.  Static Timing Analysis engines  Timing Optimization engines (buffer resizing)  Place & Route engines (net reordering, wire spreading) 30/3/10 Kostas.Kloukinas@cern.ch 18

19. Evolution of Digital Libraries More accurate Timing Libraries  Above 90nm NLDM is good enough NLDM (Non Linear Device Model) “liberty” files (.lib)  Below 90nm Current Source models in use Interconnect capacitance > cell drive impedance. Non linear switching waveforms. Input pin capacitance becomes a function slope. Current sources are more effective at tracking non-linear switching waveforms. Timing, Noise and Power calculations. ECSM (Effective Current Source Model) by Cadence CCS (Composite Current Source model) by Synopsys More Libraries due to:  Multi-V T options  Multi-voltage options  Multi-corners due to process parameters: T ox, V Th variations Interconnect variations 30/3/10 Kostas.Kloukinas@cern.ch 19

20. MMMC analysis & optimization Static Timing Analysis & Optimization  Many Modes of operation Functional modes Low Power design techniques  Process Variations Interconnect corners Device V T corners  Range of Voltage & Temperature conditions. Traditional method  Single mode/corner analysis  Design for worst case conditions  Still good for 90nm  Overdesign or non-converging solution for < 65nm. MMMC: Multi Mode Multi Corner  “Scenario” (PVT+Mode+Parasitics) based approach.  Optimization runs concurrently on all “scenarios”.  Tools identify “dominant scenarios” performing automated “scenario” reductions. 30/3/10 Kostas.Kloukinas@cern.ch 20

21. Design for Variability Process Variations  Random dopant fluctuations affecting V TH  Lithography (metalization)  Intra-die variations  Wafer- level, wafer-to-wafer, lot-to-lot variations Traditional Static Timing Analysis  Difficult to meet timimg  Too pessimistic => overdesign. Statistical Static Timing Analysis (SSTA)  RC extraction with sensitivites  Uses sensitivities to find correlations among delays.  Uses these correlations when computing how to add statistical distributions of delays.  Needs libraries supporting statistical timing 30/3/10 Kostas.Kloukinas@cern.ch 21

22. Design for Reliability IR drop refers to fluctuations of the supply voltage over the length of the supply line. For IC design we consider both static & dynamic IR drop. Electromigration  EM problems occur when the power grid is not sufficient to handle the current densities required by the design.  On the signal nets driven by high drive strength cells if the wires are too narrow,  On the power grid when several large current hungry cells are placed near to each other and are fed by inadequate power grid routing. CAE Tools  Synopsys: PrimeRail  Cadence: VoltageStorm 30/3/10 Kostas.Kloukinas@cern.ch 22 Animated voltage drop maps

23. Automated Power Grid Design PNA: Power Network Analysis  Manual Power Planning  Provides early estimation of the final sign-off analysis.  “Virtual rails” that are not simulated, only higher metal layers are considered.  “What if” analysis varying number of straps, width of straps, placement of pads, etc.  Iterations to achieve target constraints. PNS: Power Network Synthesis  Attempt to eliminate the manual work!  PN constraints describe the design targets like total IR drop, as well as provide guidelines for the layout of the grid.  PNS is quite often an iterative process.  Once the IR-drop and EM maps look ok the power plan can be committed and the physical straps and rings can actually be laid down. 30/3/10 Kostas.Kloukinas@cern.ch 23 Power Network Analysis Power Network Synthesis

24. Flip Chip Solutions RDL flow  Wirebond pads placed at the periphery.  Redistribution wiring layer to connect to ball pads. Area Array flow  Special C4 IO pads placed in designated “sites” inside the chip area.  Special short signal routing.  Special concerns for the placement of ESD structures 30/3/10 Kostas.Kloukinas@cern.ch 24

25. Design For Manufacturability Antenna Violations  To prevent damage caused by charge build-up on MOS gates (during plasma etch processing steps), which causes damage to the MOS gate oxides  If you fail to fix antenna violations, you will end up with plasma induced gate oxide damage. Max Metal Width Rules  To prevent large areas of metal from lifting off during processing due to differences in thermal co-efficient (metal and substrate will expand by different amounts)  Reduces the effects of Electro-migration.  Slotting/Cheesing wide wires or Splitting wide wires into multiple smaller wires. Pattern Density Rules  To reduce dishing and erosion of the inter-level dielectrics, requires metal lines to be at a certain minimum distance from each other (metal density). This leads to the so called metal fills (dummy metal) 30/3/10 Kostas.Kloukinas@cern.ch 25 The cause of many design Tape Out delays! Early consideration of pattern density rules is essential.

26. Layout Sign-Off Tools 30/3/10 Kostas.Kloukinas@cern.ch 26

27. IDESA - IC Design Skills for Advanced DSM Technologies © IDESA 2007 | Sign-off Evolution: Growing Importance of Sign-off Example 1X Complexity 30-40X complexity 180nm 130nm 90nm 65nm Design ScheduleDesign Schedule Variability Due to Sign-off Future Project – 40  32nm ? Should be predictable Conservative design

28. Analog & Mixed Signal Flows 30/3/10 Kostas.Kloukinas@cern.ch 28 The Concept The use of the workflows may vary depending on the design requirements and organization of design teams. Top-Down Functional Design Early chip level verification strategy has to be in place and validated with correct partitioning between analog and digital. As the project is proceeding toward completion, the same top-level validation is done by replacing the behavioural model with a transistor-level description (including RC parasitic if required). Top-Down Physical Design Early floorplanning (including pad placement) even with rough estimation of block (area, aspect ratio, pin location) will enable to plan for special nets routing (buses, clocks, power network, sensitive nets...). As the project is proceeding toward completion, the same floorplanning could be refined and adapted. Bottom-up Block Function & Physical Design Analog and Digital block circuit level implementation (transistors & gates)

29. Advanced CAE tools platform. Full-Custom Analog design  Cadence Virtuoso platform  “Front End design flow” Standard-cell Digital design  Cadence SOC Encounter platform  “Back End design flow” Key Technology: Open Access database  A common database to save & restore designs from Virtuoso and SOC_Encounter platforms.  Significantly reduces data translations and associated errors.  Open standard. (http://openeda.org) 30/3/10 Kostas.Kloukinas@cern.ch 29

30. “Analog on Top” Design Flow 30/3/10 Kostas.Kloukinas@cern.ch 30 SOC_Encounter Digital block creation SOC_Encounter Digital block creation Virtuoso Chip assembly Virtuoso Chip assembly For big ‘A’ small ‘D’ designs. Begin Finish

31. Virtuoso Floorplanning Generate Physical Hierarchy. Early in design phase: from soft-block (abstract) to hard-block (layout) Helps avoid late-in-cycle block resizing, reshaping, pin-shuffling. Cut down design cycle time with continuous and iterative floorplanning. Accurate area estimation. Full connectivity view (instances, connectivity, pins & prboundary) Partial layout view generation (abstract like) 30/3/10 Kostas.Kloukinas@cern.ch 31

32. AMS Designer Simulator Mixed-signal, mixed-language, mixed-level simulator.  Verilog¨, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS, System-C, System-Verilog, SPICE, and Spectre languages Component-level schematics, netlists, behavioral models, structural models A single-executable simulator incorporating the fastest in digital simulation (NCSim) with a choice of analog solvers (Spectre and UltraSim¨).  UltraSim provide FastSPICE simulation capability. Built on the INCA (Interleaved Native Compiled Architecture) platform. High performance  Fewer interfaces between tools  Small, efficient memory footprint Unified Debugging environment 30/3/10 Kostas.Kloukinas@cern.ch 32

33. Constraint driven Analog design 30/3/10 Kostas.Kloukinas@cern.ch 33

34. “Digital on Top” Design Flow 30/3/10 Kostas.Kloukinas@cern.ch 34 SOC_Encounter Chip Design SOC_Encounter Chip Design Virtuoso Analog Block Creation Virtuoso Analog Block Creation For big ‘D’ small ‘A’ designs. RTL synthesis Floorplanning & power routing Placement Congestion analysis Logical Equivalence Checking Timing optimization Signoff RC extraction Timing analysis DRC DFM LVS Logical Equivalence Checking Clock tree synthesis Routing Timing optimization Tape-out Automated task User task

35. 30/3/10 Kostas.Kloukinas@cern.ch 35 IC design CAE tools at CERN

36. Objectives At present, Support for two advanced technology nodes: Development of:  “CMOS8RF Mixed Signal Design Kit”  “Analog & Mixed Signal Methodologies (Workflows)” Provide:  Maintenance  Training  Support 30/3/10 Kostas.Kloukinas@cern.ch 36 CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-DM Low cost technology for Analog & RF designs CMOS 8RF-DM Low cost technology for Analog & RF designs BiCMOS 8WL Cost effective technology for Low Power RF designs BiCMOS 8HP High Performance technology for demanding RF designs BiCMOS 8HP High Performance technology for demanding RF designs CMOS 9SF LP/RF High performance technology for dense designs CMOS 9SF LP/RF High performance technology for dense designs 130nm CMOS 90nm CMOS

37. CAE Tools & Technology support 30/3/10 Kostas.Kloukinas@cern.ch 37 Foundry Physical IP vendors CAE Tools vendors CERN CAE tools & technology support Cadence VCAD design services CERN designers External designers

38. CMOS8RF Mixed Signal design kit 30/3/10 Kostas.Kloukinas@cern.ch IBM Standard cell libraries IBM PDK Mixed Signal Design Kit Mixed Signal Design Kit CAE Tools Key Features: IBM PDK V1.6 IBM Standard cell and IO pad libraries Physical Layout views available. Access to standard cell libraries is legally covered by already established IBM CDAs New versions of CAE Tools Open Access database support. Interoperability of Virtuoso and SOC-Encounter platforms. Compatible with the “Europractice” distributions. Support for LINUX Platform (qualified on RHEL4) Two design kits available: CMOS8RF-DM (3-2-3 BEOL) CMOS8RF-LM (6-2 BEOL) 38

39. CMOS8RF Mixed Signal Workflows 30/3/10 Kostas.Kloukinas@cern.ch Design Workflows Digital Library PDK Analog & Mixed Signal (AMS) Workflows.  Formalize the design work by employing standardized and validated Design Workflows.  Formalize the design work across design teams in common projects.  Provide a repository with reference design examples. Development work subcontracted to Cadence, VCAD design services. Close collaboration of CERN - VCAD - IBM  VCAD brought in their invaluable expertise on the CAE tools  IBM provided the physical IP blocks and important technical assistance  CERN assisted the development and validated the design kit functionality. 39

40. Analog & Mixed Signal Workflows 30/3/10 Kostas.Kloukinas@cern.ch 40

41. 30/3/10 Kostas.Kloukinas@cern.ch 41 Digital Block Implementation Flow Prepared by Sandro Bonacini CERN PH/ESE sandro.bonacini@cern.ch “I 2 C slave” serial interface IP block employing Triple Module Redundancy for enhanced SEU protection.

42. 30/3/10 Kostas.Kloukinas@cern.ch 42 RTL synthesis Floorplanning & power routing Placement Congestion analysis Logical Equivalence Checking Timing optimization Signoff RC extraction Timing analysis DRC DFM LVS Logical Equivalence Checking Clock tree synthesis Routing Timing optimization Tape-out Automated task User task Digital Design Flow

43. Synthesis 30/3/10 Kostas.Kloukinas@cern.ch 43 RTL compiler script [.tcl] Abstract layout Definition [.lef] Capacitance tables [.CapTbl] Max timing Liberty libraries [.lib] RTL synthesis RTL description [.v] / [.vhd] Timing constraints [.sdc] Mapped netlist [.v] Conformal script [.lec] Synthesis, mapping and timing reports sandro.bonacini@cern.ch

44. Logic Equivalent Checking (LEC) 30/3/10 Kostas.Kloukinas@cern.ch 44 Tool: Conformal Logical Equivalence Checking Max timing Liberty libraries [.lib] Mapped netlist [.v] Conformal script [.lec] RTL description [.v] / [.vhd] LEC report sandro.bonacini@cern.ch

45. Floorplanning & Power Routing 30/3/10 Kostas.Kloukinas@cern.ch 45 Define  Chip/core size  target area utilization  I/O placement  module placement in case of TMR or other special constraints Power planning/routing  Core/block rings and stripes sandro.bonacini@cern.ch

46. Placement 30/3/10 Kostas.Kloukinas@cern.ch 46 Encounter command file Placement Scan-chain reorder Open Access Floorplanned Design [.oa] Connect cells power/ground Add tap cells Open Access Placed Design [.oa] Reports sandro.bonacini@cern.ch

47. Placement 30/3/10 Kostas.Kloukinas@cern.ch 47 Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Power/ground connections Tap cells Standard cells sandro.bonacini@cern.ch

48. Congestion analysis 30/3/10 Kostas.Kloukinas@cern.ch 48 Use Encounter Trialroute to estimate congested areas Manually add placement partial blockage Change position of I/Os or blocks …or increase number of routing metals Open Access Placed Design [.oa] Congestion analysis Placement optimization Open Access Placed Design [.oa] sandro.bonacini@cern.ch

49. Clock tree synthesis & signal routing 30/3/10 Kostas.Kloukinas@cern.ch 49 sandro.bonacini@cern.ch

50. Design For Manufacturing 30/3/10 Kostas.Kloukinas@cern.ch 50 Signoff RC extraction Cells & metal fill Open Access Routed Design [.oa] Antenna fix Via optimization Timing analysis Open Access Final Design [.oa] Signoff timing report Delay file [.sdf] Final netlist [.v] Signal integrity analysis sandro.bonacini@cern.ch

51. Antenna fix 30/3/10 Kostas.Kloukinas@cern.ch 51 Re-routes long nets Inserts tie-down diodes sandro.bonacini@cern.ch

52. Via optimization 30/3/10 Kostas.Kloukinas@cern.ch 52 sandro.bonacini@cern.ch

53. Filler cells and metal fill 30/3/10 Kostas.Kloukinas@cern.ch 53 sandro.bonacini@cern.ch

54. Back to Virtuoso ! 30/3/10 Kostas.Kloukinas@cern.ch 54 OA design is present in Virtuoso  Easily included in a mixed-signal chip sandro.bonacini@cern.ch

55. Training: AMS Workshops Workshop Targets:  Present the IBM CMOS8RF (130nm) Mixed Signal Kit.  Present Workflows for Analog, Digital and Mixed Signal designs.  Introduce the new Platform of Cadence CAE Tools. This is NOT:  A course on analog or digital designing.  An advanced course targeted to a specific Cadence Tool. 30/3/10 Kostas.Kloukinas@cern.ch 55

56. Example Design The workshop modules are based on a realistic Mixed Signal ASIC:  Analog IP block: DAC  Digital IP block: SRAM  Digital block: I2C slave synthesizable RTL code Triple Module Redundancy  Digital Flow Scripts Top level Behavioral Modeling Design verification Final chip Physical verification 30/3/10 Kostas.Kloukinas@cern.ch 56

57. AMS Workshop Contents Day 1 (Lead by Maxime Barbe) - Introduction to AMS kit Workshop - Functional Verification : Digital Simulation Flow - Functional Verification : AMS Simulation from command-line - Functional Verification : AMS Simulation from DFII Day 2 (Lead by Maxime Barbe) - Analog IP Characterization : ADEXL - Overview of IC6.13 (ADEXL and VSE) - Analog Block Creation: Constraints Day 3 (Lead by Vincent Cao Van Phu) - Hierarchical Floorplaning (Virtuoso based) - CDB IP Import to OA database for IC61 Methodology Day 4 (Lead by Vincent Cao Van Phu) - Digital Block Implementation - Block IP Characterization Back End - Digital IP Characterization Front-End Day 5 (Lead by Vincent Cao Van Phu) - Constraint Driven Analog Block Creation Back-End - DRC (Calibre + Assura workflows) - LVS (Callibre + Assura workflows) - Extraction - Round table discussion and workshop evaluation (30min). 30/3/10 Kostas.Kloukinas@cern.ch 57 Analog & Mixed Signal Digital Physical Verification

58. AMS Workshops Workshop sessions 1 st session: 26/10 – 30/10, 2009 (CERN internal engineers, “pilot” run) 2 nd session: 16/11 – 20/11, 2009 (CERN, open to external engineers) 3 rd session: 30/11 – 4/12, 2009 (IPHC, Strasbourg, France) 4 th session: 1/2 – 5/2, 2010 (CERN, with fees) 5 th session: 15/2 – 19/2, 2010 (CERN, with fees) 6 th session: 1/3 – 5/3, 2010 (CERN, with fees) 7 th session: 12/4 – 16/4, 2010 (CERN, with fees) Statistics 10 engineers/session. 70 engineers in total. Support Technical: Bert Van Koningsveld Secretarial: Evelyne Dho 30/3/10 Kostas.Kloukinas@cern.ch 58

59. Future Plans Extend the functionalities of the CMOS8RF (130nm) kit.  Next PDK release scheduled for 3Q 2010 Integrates PDK V1.7.0 Implements bug fixes as reported by users. Development of a Design Kit for the CMOS9LP/RF (90nm)  Standard cell libraries.  Design Workflows similar to those in the CMOS8RF Design Kit. IP Block Packaging Solution 30/3/10 Kostas.Kloukinas@cern.ch 59

60. IP packaging solution (VCAD) 30/3/10 Kostas.Kloukinas@cern.ch 60

61. DECM tool in use at CERN D esign E nvironment C onfiguration M anagement  Workflow management tool  Design environment configuration (environment variables, startup files, tool paths, etc)  CAE tools rely heavily on UNIX environment variables for their configuration. Centralized management:  Customized design environment for each project  Consistency of setup within the design team  Stability  Project versioning Flexibility  Easy Graphical User Interface for the users and administrators.  Different GUIs for different user roles  Multiple sessions with different design environment configurations  Built in project access control mechanism VCAD Productivity IP solution. Administrator: Bert Van Koningsveld 30/3/10 Kostas.Kloukinas@cern.ch 61 PDKs & Libraries EDA Tools Projects Workflows Admin editor Project editor Project users DECM server

62. RAID Server CAE Server #1 Users Workstations (LINUX PCs) lnxmic2 SUN C. Paillard lnxmic3 SUN K. Kloukinas lnxmic4 SUN S. Marchioro lnxmic5 SUN A. Rivetti lnxmic6 Cogestra L. Pierobon lnxmic7 Cogestra W. Bialas lnxmics1 DELL 1 TB RAID 1 Disc Storage lnxmic8 Cogestra P. Aspell Tivoli server CERN IT CERN ESE lnxmic9 SUN P. Moreira S. Bonacini lnxmic10 SUN W. Snoeys DAS server DELL 7 TB RAID 6 Disc Storage LINUX CAE platform for IC design STATUS: Feb. 15, 2010 30/3/10 62 Kostas.Kloukinas@cern.ch lnxmic11 Cogestra M. Marra lnxmic12 SUN G. Venturini lnxmic13 SUN J. Kaplon lnxmic14 SUN K. Poltorak lnxmic15 SUN F. Faccio lnxmic16 SUN S. Michelis lnxmic17 SUN S. Orlandi lnxmic18 SUN F. Anghinolfi lnxmic19 SUN W. Snoeys lnxmic20 Cogestra R. De Oliveira lnxmic21 HP L. Perktold lnxmic22 SUN X. Llopart lnxmicjb SUN T.S. Poikela File Backup server Administrators: Bert Van Koningsveld Wojciech Bialas

63. The CERN ASIC support website 30/3/10 Kostas.Kloukinas@cern.ch 63 http://cern.ch/asic-support Download Design Kits and access technical documents (restricted access) Information about MPW runs and foundry access services. Communicate news and User support feedback forms and access request forms. This website replaces our ‘afs’ based download facility.

64. Wrap Up A message to Industry 30/3/10 Kostas.Kloukinas@cern.ch 64 A message to industry: “ The present situation of IC design, which has high levels of flexibility in implementation is not sustainable by small and medium scale design groups and a highly structured design flow and methodologies will need to be established” Foundry 130 nm 90 nm 65 nm 45 nm Third party IP vendors Methodologies CAE Vendors

65. 30/3/10 Kostas.Kloukinas@cern.ch 65 Acknowledgements IDESA training EU 7 th Framework Program (http://www.idesa-training.org/) for material presented in slides.http://www.idesa-training.org/ Cadence & VCAD services group in Paris for material presented in slides. IBM for technology data presented in slides. Sandro Bonacini@CERN.ch, for his work on the customized digital design flow. Bert.Van.Koningsveld@CERN.ch, Wojciech.Bialas@CERN.ch, for their efforts in the CAE tools support services.

66. Sign-Off Formal Equivalence Verify that the final netlist is functionally equivalent to the original RTL code. Using formal methods to compare logic. Two representations:  Reference (Golden) RTL code, the “correct” reference design  Implementation (unknown) the design being verified. Give a pass/fail result with information to help diagnosis. 30/3/10 Kostas.Kloukinas@cern.ch 66