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Power supply and substrate noise analysis; Reference tool experience with silicon validation Yoji Bando *1*4, Daisuke Kosaka *4, Goichi Yokomizo *2, Kunihiko.

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Presentation on theme: "Power supply and substrate noise analysis; Reference tool experience with silicon validation Yoji Bando *1*4, Daisuke Kosaka *4, Goichi Yokomizo *2, Kunihiko."— Presentation transcript:

1 Power supply and substrate noise analysis; Reference tool experience with silicon validation Yoji Bando *1*4, Daisuke Kosaka *4, Goichi Yokomizo *2, Kunihiko Tsuboi *2, Ying Shiun Li *3, Shen Lin *3, Makoto Nagata *1*4 Kobe University *1, STARC *2, Apache Design Solutions, Inc. *3, A-R-Tec Corp. *4

2 DAC2009-UT#8.2 -2- Power supply (PS) noise impacts on circuits - digital: timing variation, leakage increase - analog-MS: substrate crosstalk, substrate coupling Digital PS integrity technology, with enhancements of substrate coupling/noise analysis On-chip measurements connect EDA analysis with reality Motivation

3 DAC2009-UT#8.2 -3- Multi-party collaboration for validated noise analysis Chip designer, IP provider, EDA tool provider Fully integrated power and substrate noise analysis A high capacity solver for a single large matrix unifying on-chip power grids and current sources, chip-level substrate meshes, and off-chip board networks On-chip noise measurements for silicon correlation Noise monitors with very many probing channels for thorough correlation of simulation and measurements Technical contribution

4 DAC2009-UT#8.2 -4- Multi-party collaboration for confidence noise analysis Power library: Logic cell characterization Dynamic and static PS noise analysis Substrate network and noise analysis Verification planning and test chip design On-chip noise meas. and correlation Physical design and sign-off flow Integrity design tool developer (cf. Apache Design Solutions) Integrity design consultant (cf. A-R-Tec) User company (cf. IDM, design house)

5 DAC2009-UT#8.2 -5- Key technology contributions #1 PSA and SNA Power library: Logic cell characterization Dynamic and static PS noise analysis Substrate network and noise analysis Verification planning and test chip design On-chip noise meas. and correlation Physical design and sign-off flow

6 DAC2009-UT#8.2 -6- Key technology contributions #2 Simulation and Silicon correlation Power library: Logic cell characterization Integrated PS and substrate noise simulation Verification planning and test chip design On-chip noise measurements Physical design and sign-off flow

7 DAC2009-UT#8.2 -7- Substrate noise probe array in left top area PS noise probe array for 32-bit  P 5.0 mm 32-bit  P core SRAM macros Noise evaluation chip overview Substrate noise probe array in right btm. area A 32-bit processor (SH-4*) with 210 kB memory capacity Densely distributed on-chip dynamic noise monitors 90-nm CMOS, 5LM, 1.0 V technology SH-4* Renesas technology

8 DAC2009-UT#8.2 -8- Noise probing locations in  P core 32-bit uP core 2.5 mm 2.0 mm

9 DAC2009-UT#8.2 -9- Noise probing locations on substrate P + GR (guard ring) deep Nwell GR P + probing points 1.6 mm 0.5 mm Substrate noise evaluation area (120 probing points in total) deep Nwell pocket

10 DAC2009-UT#8.2 -10- On-chip noise monitor circuitry Off-chip n-SF p-SF Vout Digital Vdd Gnd Iout p-SF n-Gm p sub Vout Substrate (P+) noise probing array PS noise probing array On-chip

11 DAC2009-UT#8.2 -11- Probing @SH-4 center, Fclk = 50 MHz PS noise waveform measurements Vdd Gnd 0.94 0.96 0.98 1.00 200 nsec -0.02 -0.01 0.00 0.01 0.02 Voltage (V)

12 DAC2009-UT#8.2 -12- 0 20 40 60 80 #1 #2#3#4#5#6#7#8#9 #10#11#12#13#14#15#16#17#18#19#20#21#22#23#24#25#26#27#28#29#30#31#32#33#34#35#36#37#38#39#40 V (mV) 0 10 20 30 40 uP Vdd Static drop Dynamic Vpp uP Gnd Static drop Dynamic Vpp # test code with higher level of internal logic activity PS noise intensity: code dependence Vnominal Static drop Dynamic Vpp Voltage

13 DAC2009-UT#8.2 -13- Unified matrix of chip-level noise analysis Vdd/Gnd grids PS current sources Vertical impurity profile Off-chip networks Silicon substrate model Resistive as well as capacitive elements involved (e.g. pwell, nwell, deep well)

14 DAC2009-UT#8.2 -14- Full chip PS and substrate noise analysis: flow overview SoC Layout LEF/DEF Macro Geometry GDSII Macro Netlist spice netlist Cell Library.lib, spice Totem_SE Extraction, Simulation Pkg Model RLC or S-Para Debugging, What-if and FAO RedHawk-EV Substrate Model Digital Technology file

15 DAC2009-UT#8.2 -15- Noise source modeling Apache Power Library (APL) - SPICE simulation: I(t) LUT for in/out condition, load caps - Post-layout extraction logic cell level: Cesc, Resr Standard cell library (LEF/DEF) Vss wiring Vdd wiring well network C esc I(t) R esr C pg Cwell

16 DAC2009-UT#8.2 -16- Substrate network modeling

17 DAC2009-UT#8.2 -17- Off-chip network modeling L C Off-chip power delivery network (PDN) - FR4 board, package, bonding wires – macroscopically seen by a chip - Lumped LCR extraction between Vdd and Gnd terminals - Considerable impacts on noise components from DC to a few 100 MHz

18 DAC2009-UT#8.2 -18- Unified matrix for quality noise analysis Substrate coupling analysis enhances accuracy of noise analysis in digital as well as mixed-signal circuits. Ground noise in SH-4 processor @ 50 MHz, comparing simulation with on-chip measurements 2 3 4 5 1 SH-4 core only w/ off-chip model 45 50 55 60 65 75 0246 V gnd-pp (mV) Probe point 80 meas. w/ off-chip and substrate models 70 w/o off-chip model w/o substrate model

19 DAC2009-UT#8.2 -19- Dynamic PS noise waveforms 0.90 0.92 0.94 0.96 0.98 1.00 (V) -0.02 0.00 0.02 0.04 0.06 0.08 (V) 100406080200(ns) 100406080200(ns) Vdd noise @ Fck = 50 MHz Gnd noise @ Fck = 50 MHz Measured Simulated

20 DAC2009-UT#8.2 -20- Gnd/Psub noise: chip-wide Vpp map Simulated drop of uP Gnd/Psub @ Fck = 50 MHz Measured, left top Measured, right bottom 40 (mV) 30 20 10 0 500 600 700 800 900 1000 y(  m) -1600-1400-1200-1000-800-600-400-200 x(  m) -500 -600 -700 -800 -900 -1000 y(  m) -1600-1400-1200-1000-800-600-400-200 x(  m) 0 30 (mV) 20 10 0 yLyR xU xL

21 DAC2009-UT#8.2 -21- Substrate noise (Vpp) trend: yL axis Distance (mm) -2.00.01.0 uP GndPsub Vpp (mV) sim. y-left (yL) meas. 0 20 40 60 yLyR xU xL Fck = 50 MHz

22 DAC2009-UT#8.2 -22- Substrate noise (Vpp) trend: xL axis yLyR xU xL 2.0 0.01.0 uP GndPsub Distance (mm) Vpp (mV) 0 20 40 60 sim. x-lower (xL) meas. Fck = 50 MHz

23 DAC2009-UT#8.2 -23- Cost of Simulation Chip to simulate Mesh size CPU time Memory usage Machine spec. SH-4 core: 670k gates, SRAM cells: 11.2M trs., # of I/O: 208 pins, chip area: 5.0 mm x 5.0 mm 750 k extraction 1.0 h, simulation 1.5 h (for 120 nsec) extraction 6.6 GB, simulation 3.5 GB 2-core Opteron x 2 @ 2.8GHz, 64 GB memory

24 DAC2009-UT#8.2 -24- Summary Unification of on-chip power grids, substrate, and off-chip network realizes dynamic PS and substrate noise simulation with high accuracy Comprehensive on-chip noise measurements establish reference experience of silicon validation Close correlation of simulation and measurements achieves designers’ confidence of noise analysis

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