1. Institute of Experimental and Applied Physics Czech Technical University in Prague 11th December 2007 Michal Platkevič RUIN Rapid Universal INterface for Medipix

2. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Work in UTEF April 2006 – half-time November 2006 – full-time Work: RUIN – Rapid Universal INterface PCB for stepper motors control Prototype of USB1 modification for Timepix Spectroscopic modul ATLAS – Medipix wirring Measurement on PALS Measurement of slow neutrons in ILL Diploma thesis (June 2007): Signal processor controlled USB2.0 interface for Medipix2 detector Presentations: USB2.0 Interface Status (CERN) Signal processor controlled USB2.0 interface for Medipix2 detector (IWORID 9) Status of USB interfaces (MidSweden University) Medipix /ATLAS – wiring ( CERN) Medipix in an extremely hostile environment (CERN) USB2.0 interface for Medipix2 device (CERN)

3. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič (Si) Amplifier Compa- rator Counter: Particle count 000001 Pixel electronics + Bias Voltage Threshold level Threshold level above electronic noise  No false counting. Digital integration (counting)  No dark current. Unlimited dynamic range and exposure time. Detected count obeys poissonian distribution Planar pixellated detector (Si, GaAs, CdTe) is bump- bonded to read-out chip Ionizing particle creates a charge in a sensitive volume The charge is amplified and compared with a threshold Digital counter is incremented. Medipix2 detector MEDical Imaging PIXel detector of 2nd generation Pixels: 256 x 256 Pixel size: 55 x 55  m 2 Area: 1.5 x 1.5 cm 2

4. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Medipix – data read-out The serial readout uses a LVDS port to shift out all the matrix data. In readout mode the 14-bit shift register of each pixel is connected to the next one forming a 3584-bit shift register. Communication between the pixel matrix and the IO logic is carried out through the 256-bit FSR. The number of clocks needed in order to read one chip are 917512 (256x256x14+8). External clock have to be used to shift the data from pixel to pixel. 14-bit reg. …… …… ……………… … … … … … … … … … … … … 256 pixels 14-bit reg. 3584-bit pixel column - 0 3584-bit pixel column - 1 3584-bit pixel column - 2 3584-bit pixel column - 254 3584-bit pixel column - 255 256-bit FSR … … … … … … … … … … bit …… LVDS Input LVDS Output IO Logic 32-bit CMOS Output

5. Faculty of Nuclear Sciences and Physical Engineering Czech Technical University in Prague IEAP – CTU Prague New Interface - Design strategy New interface design puts emphasis on: Speed of data read-out. (maximum speed possibility of the Medipix serial read-out: currently 200 MHz) Support for all chips of MPX family USB2.0 Ethernet DSP Medipix chipboard Memory Power supplies FPGA PC and Power supply PC and Power supply Strategy : Conecting with PC USB2.0 - transfer rate of 480 Mb/s 1Gb/s Ethernet Usage of the digital signal processor High data throughput High computational performance (up to 8000 mips), even sophisticated data processing can be done here (threshold equalization, flat field correction, cluster analysis, data compression …) Built in management of large memory Usage of the FPGA Hardware de-serialization of the serial data - decrease a processor load I/O - LVDS, CMOS Flexibility – possibility to change functionality without need of hardware modification New interface 11th December 2007 Michal Platkevič

6. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Principle of Data Read-out The serial data from the Medipix are shifted to fast shift registers When the registers are filled up, the parallel data are loaded to the latch. DSP reads the data from the latch via the data bus Individual chips of multichip assembly are read out simultaneously. Shift register is arranged as a 4 eight bit segments. Each segment can be fed from separate MPX chip. Usage of multiple latches in form of FIFO could be advantageous 32 bits Memory PLL clock generator + control logic PLL clock generator + control logic USB 2.0 8 bits Shift reg. 8 bits Shift reg. LATCH 32 bits Memory PLL clock generator + control logic PLL clock generator + control logic USB 2.0 8 bits Shift reg. 8 bits Shift reg. LATCH Shift reg. 32 bits Memory PLL clock generator + control logic PLL clock generator + control logic USB 2.0 8 bits Shift reg. 8 bits Shift reg. LATCH Shift reg. 32 bits Memory PLL clock generator + control logic PLL clock generator + control logic USB 2.0 8 bits Shift reg. 8 bits Shift reg. LATCH Shift reg.

7. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Status Current prototype fully tested with MXR chip (up to 48 MHz) Schematic design is finishing PCB design will be ordered soon … DSP evaluation board FPGA evaluation board Power supply for Medipix Medipix

8. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Interface Layout Power USB Header DSP FPGA Flash Memory DDR2 RJ45 Cypress DAC 8x Memory DDR2 ADC 8x Ethernet Power Connectors Power Mini USB General purpose 20 pin header Ethernet Connectors Power Mini USB General purpose 20 pin header Ethernet Power supply PCB For Medipix For interface Power connector Power supply PCB For Medipix For interface Power connector Logic DSP (TI) FPGA (Lattice) USB (Cypress) Ethernet (Intel) DDR2 memory Flash memory Logic DSP (TI) FPGA (Lattice) USB (Cypress) Ethernet (Intel) DDR2 memory Flash memory Inner Connectors JTAG for DSP FPGA programming General purpose Power Medipix Power for Medipix Inner Connectors JTAG for DSP FPGA programming General purpose Power Medipix Power for Medipix Changeable Medipix chipboard adapter To be more flexible we decided to use modular system

9. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Interface Layout DSP FPGA Ether net Flash Memory DDR2 RJ45 USB Cypre ss ADC 8x DAC 8x Power 6 cm 14 cm Power Changeable chipboard adapter is recognized automatically and LVDS and CMOS pins of FPGA are configured. All signals from Medipix go via the FPGA (Lattice XP) with configurable inputs outputs – LVDS, CMOS Debugging

10. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Supported Detectors Detectors Medipix2, Medipix MXR Medipix Quad (daisy chain or separately) Timepix … Medipix3 Read-out: Serial Parallel Connecting: Directly/via the cable CMOS/LVDS

11. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič unused CMOS 16b LVDS 8pairs Data read-out and control Bank 2 Bank 3 Bank 6 Bank 7 FPGA Medipix2, MXR, Timepix - 100 fps at 100 MHz Serial data Control LVDS - 6 pairs Enable_OUT Enable_IN Data_OUT Data_IN Clk_IN Clk_OUT CMOS 10 control bits LVDS - 6 pairs Enable_OUT Enable_IN Data_OUT Data_IN Clk_IN Clk_OUT CMOS 10 control bits DSP data bus 32 bits x 133 MHz 4.256 Gb/s Medipix chipboard Adapter board

12. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič unused CMOS 16b LVDS 8pairs Data read-out and control Standard Quad - 25 fps at 100 MHz Serial data Control LVDS - 6 pairs Enable_OUT Enable_IN Data_OUT Data_IN Clk_IN Clk_OUT CMOS 10 control bits LVDS - 6 pairs Enable_OUT Enable_IN Data_OUT Data_IN Clk_IN Clk_OUT CMOS 10 control bits Bank 2 Bank 3 Bank 6 Bank 7 FPGA DSP data bus 32 bits x 133 MHz 4.256 Gb/s

13. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič LVDS 8pairs CMOS 16b LVDS 8pairs Data read-out and control Quad – each chip read separately 100 fps at 100 MHz Serial data LVDS - 24 pairs 4 x Enable_OUT 4 x Enable_IN 4 x Data_IN 4 x Data_OUT 4 x Clk_IN 4 x Clk_OUT CMOS 10 control bits LVDS - 24 pairs 4 x Enable_OUT 4 x Enable_IN 4 x Data_IN 4 x Data_OUT 4 x Clk_IN 4 x Clk_OUT CMOS 10 control bits Control Bank 2 Bank 3 Bank 6 Bank 7 FPGA DSP data bus 32 bits x 133 MHz 4.256 Gb/s Serial data

14. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič CMOS 16b LVDS 8pairs Data read-out and control Medipix2, MXR, Timepix -parallel read-out -3200 fps at 100 MHz Serial data Parallel data 32b LVDS - 5 pairs Enable_OUT Enable_IN Data_IN Clk_IN Clk_OUT CMOS 10 control bits Parallel data LVDS - 5 pairs Enable_OUT Enable_IN Data_IN Clk_IN Clk_OUT CMOS 10 control bits Parallel data Control Bank 2 Bank 3 Bank 6 Bank 7 FPGA DSP data bus 32 bits x 133 MHz 4.256 Gb/s

15. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič LVDS 8pairs CMOS 16b LVDS 8pairs Data read-out and control 4 x standard Quad 25 fps at 100 MHz Control LVDS - 24 pairs 4 x Enable_OUT 4 x Enable_IN 4 x Data_IN 4 x Data_OUT 4 x Clk_IN 4 x Clk_OUT CMOS 10 control bits LVDS - 24 pairs 4 x Enable_OUT 4 x Enable_IN 4 x Data_IN 4 x Data_OUT 4 x Clk_IN 4 x Clk_OUT CMOS 10 control bits Bank 2 Bank 3 Bank 6 Bank 7 FPGA DSP data bus 32 bits x 133 MHz 4.256 Gb/s Serial data

16. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Finding name R apid U niversal IN terface RUIN R U IN

17. Institute of Experimental and Applied Physics Czech Technical University in Prague IEAP – CTU Prague 11th December 2007 Michal Platkevič Thank you for your attention!