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Cumulative Design Review: Interactive Teaching Device April 8 th, 2005 Lance Haney Micah Nance Nathan Young.

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Presentation on theme: "Cumulative Design Review: Interactive Teaching Device April 8 th, 2005 Lance Haney Micah Nance Nathan Young."— Presentation transcript:

1 Cumulative Design Review: Interactive Teaching Device April 8 th, 2005 Lance Haney Micah Nance Nathan Young

2 Important Persons Client –Dr. Aaron Collins Technical Advisor –Dr. John Reece Project Manager –Dr. Phillip Olivier

3 Overview PDR Review Delivered Design –Hardware –Software DemonstrationBudgetConclusionRecommendations

4 Client Requirements Update ECE 424 and ECE 426 Use state of the art technology Prepare for new industry trends Deliver teaching device Deliver lab manual

5 Feasibility Criteria Low budget ($300 maximum) Compatible with Win98 or WinXP Applicable to ECE 424 and ECE 426

6 PDR Design Alternatives SOPC with RTOS SOPC without RTOS Microcontroller with RTOS Microcontroller without RTOS VHDL

7 Design Selected - PDR Phase Selected SOPC with RTOS Design NIOS II Evaluation Edition –MicroC/OS-II feature disabled Design Change –SOPC without RTOS Design Addition –Implemented VHDL Design

8 Why SOPC? One chip –Simplified design –Less hardware Supports VHDL & current curriculum Nios II Soft-core Processor –C/C++ –Assembly Expedite upgrades

9 Delivered Design VHDL Implementation SOPC with Nios II UP3 Development Board External Hardware Assembly Lab Manual

10 UP3 Development Board Cyclone FPGA External RAM On Board Pushbuttons On Board LEDs LCD Display Expansion Headers Parallel Port Serial Port USB Port VGA Port RAM -11.25 KB on-chip -128 KB external 48 MHz clock

11 External Hardware Assembly

12 Delivered System

13 VHDL –Efficient use of logic elements –1% Logic Elements Used Nios II Soft-core Processor with C code –Embedded Processor –High Level Language –33% Logic Elements Used –49% Total On-chip Memory Used System Implementation Alternatives

14 VHDL Design

15 C Code Software Design

16 Nios II Configurations

17 Nios II Debugging Options

18 System Demonstration VHDL Design Nios II Soft-core Processor with C Code Design

19 Budget Prototype Cost PartQuantityPrice per unitSubtotal UP3 Development Board1$0.00 Altera Software1$0.00 IDE Cable1$5.00 LEDs (1.8V@20mA)30$0.20$6.00 Resistors (150 Ohm)30$0.20$6.00 Resistors (10k Ohm)30$0.20$6.00 Mushroom Pushbutton Switch2$18.01$36.02 Jumper Wires1$11.25 Breadboard1$8.78 Mount - Wooden Box1$8.00 Tax (7%)$6.09 Total$93.14

20 PartAllied Electronics #QuantityPrice per unitSubtotal UP3 Board 12$249.00$2,988.00 IDE Cable 12$5.00$60.00 LEDs (1.8V@20mA)431-0152120$0.15$18.00 Resistors (150 Ohm)296-5952120$0.35$42.00 Resistors (10k Ohm)296-652660$0.25$15.00 Mushroom Pushbutton Switch814-002224$18.01$432.24 Jumper Wires (75 count)618-346412$10.00$120.00 Breadboard761-001012$19.50$234.00 Tax (7%)$273.65 Total$4,182.89 Budget Lab Implementation

21 Conclusion Utilize Altera UP3 Development Board –Low cost –Versatile –Expandable –Innovative Altera Software Package –Reasonable learning curve –User friendly –Versatile

22 Recommendations 12 Workstations –Altera UP3 Development Board –External Hardware –Windows XP Integration into ECE 424/426 curriculum

23 Summary PDR Review Delivered Design DemonstrationBudgetConclusionRecommendations

24 Questions?


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