1. Bus-Based Computer Systems zBusses. zMemory devices. zI/O devices zDesigning with microprocessors. zDevelopment and debugging. zSystem-level performance analysis. 1

2. 8/25/2015 The CPU bus zBus allows CPU, memory, devices to communicate. yShared communication medium. zA bus is: yA set of wires. yA communications protocol. xProtocols are specified by state machines. xasynchronous logic behavior 2

3. 8/25/2015 Four-cycle handshake ( 四周期握手协议 ) device 1device 2 enq ack time device 1 device 2 1234 3

4. 8/25/2015 Four-cycle handshake, cont’. 1.Device 1 raises enq. 2.Device 2 responds with ack. 3.Device 2 lowers ack once it has finished. 4.Device 1 lowers enq. 4

5. Microprocessor busses 8/25/2015 5

6. Bus read and write 6

7. 8/25/2015 State diagrams for bus read CPU device Get data Done Adrs Wait See ack Send data Release ack Adrs Wait Ack start 7

8. 8/25/2015 Bus wait state 8

9. 8/25/2015 Bus burst read( 总线突发读 ) 9

10. Disconnected transfers ( 非连接传输 ) zThe request and response are separate. yA first operation requests the transfer yThe bus can then be used for other operations yWhen the data are ready, the transfer is completed later. 10

11. Small data bundles zReduce the cost of the chip. zHow to form the data or address yAssembled inside the CPU’s bus logic before being presented to the CPU proper. 11

12. 8/25/2015 Bus multiplexing （多路复用） CPU adrs device data adrs data enable Adrs enable 12

13. DMA （直接存储器访问） zDirect memory access (DMA) performs data transfers without executing instructions. yCPU sets up transfer. yDMA engine fetches, writes. zDMA controller is a separate unit. 8/25/2015 13

14. DMA （直接存储器访问） 8/25/2015 14

15. Bus mastership （总线主控器） zBy default, CPU is bus master and initiates transfers. zDMA become bus master to perform its work. yCPU can’t use bus while DMA operates. zBus mastership protocol:(Four-cycle handshake protocol) yBus request. yBus grant. 8/25/2015 15

16. DMA operation zCPU sets DMA registers for start address, length. zDMA status register controls the unit. zOnce DMA is bus master, it transfers automatically. yMay run continuously until complete. yMay use every n th bus cycle. 8/25/2015 16

17. System bus configurations zMultiple busses allow parallelism: ySlow devices on one bus. yFast devices on separate bus. zA bridge connects two busses. 8/25/2015 CPUslow device memory high-speed device bridge slow device 17

18. 8/25/2015 Bridge state diagram 18

19. ARM AMBA bus zTwo varieties: yAHB is high-performance. yAPB is lower-speed, lower cost. zAHB supports pipelining, burst transfers, split transactions, multiple bus masters. zAll devices are slaves on APB. 8/25/2015 19

20. ARM AMBA bus 8/25/2015 20

21. Memory components zEach type of memory comes in varying: yCapacities. yWidths. zFor a memory of a given size, there are several versions y256Mb x64M*4 x32M*8 8/25/2015 21

22. I/O devices zKeyboard zLed zDisplay y7-segment yLCD yTouchscreen zTimer and counter zA/D, D/A 22

23. 8/25/2015 Keyboard--- Switch debouncing zA switch must be debounced to multiple contacts caused by eliminate mechanical bouncing: 23

24. 8/25/2015 Encoded keyboard zAn array of switches is read by an encoder. zN-key rollover remembers multiple key depressions. row 24

25. 8/25/2015 LED( 发光二极管 ) zMust use resistor to limit current: 25

26. display zDisplay yDirectly driven xSingle-digit display consists of seven segments yFrame buffer( 帧缓冲区 ) xLarge display 26

27. 8/25/2015 7-segment LCD display zMay use parallel or multiplexed input. 27

28. 8/25/2015 Types of high-resolution display zLiquid crystal display (LCD) is dominant form. zPlasma( 等离子 ), zOrganic Light-Emitting Diode ； OLED ( 有机发光 二极管显示面板 ), etc. zFrame buffer holds current display contents. yWritten by processor. yRead by video. 28

29. 8/25/2015 Touchscreen( 触摸屏 ) zIncludes input and output device. zInput device is a two-dimensional voltmeter: 29

30. 8/25/2015 Touchscreen position sensing ADC voltage 30

31. Timers and counters （定时 器和计数器） zVery similar: ya timer is incremented by a periodic signal; ya counter is incremented by an asynchronous, occasional signal. zRollover causes interrupt. 31

32. Watchdog timer( 监视定时器 ) zWatchdog timer is periodically reset by system timer. zIf watchdog is not reset, it generates an interrupt to reset the host. host CPU watchdog timer interrupt reset 32

33. 8/25/2015 Digital-to-analog conversion zInterface: only the data value zThe input value is continuously converted to analog form 33

34. 8/25/2015 A/D conversion zTypes of A/D converter circuits yA constant amount of time yVariable-time converters provide a done signal so that the microprocessor knows when the value is ready. zInterface: yAnalog inputs yTwo major digital input: xA data port allows A/D registers to be read and written xA clock input 34

35. 8/25/2015 System architectures zArchitecture: a set of elements and the relationships between them that together form a single unit. zArchitectures and components: ysoftware; yhardware. zSome software is very hardware- dependent. 35

36. 8/25/2015 Hardware platform architecture Contains several elements: zCPU; zbus; zmemory; zI/O devices: networking, sensors, actuators, etc. How big/fast much each one be? 36

37. 8/25/2015 Software architecture Functional description must be broken into pieces: zdivision among people; zconceptual organization; zperformance; ztestability; zmaintenance. 37

38. 8/25/2015 Hardware and software architectures Hardware and software are intimately related: zsoftware doesn’t run without hardware; zhow much hardware you need is determined by the software requirements: yspeed; ymemory. 38

39. 8/25/2015 Evaluation boards( 评估板 ) zDesigned by CPU manufacturer or others. zIncludes CPU, memory, some I/O devices. zMay include a serial link for downloading programs. zCPU manufacturer often gives out evaluation board netlist( 网表 ) and board layout---can be used as starting point for your custom board design. 39

40. 8/25/2015 Adding logic to a board zProgrammable logic devices (PLDs) provide low/medium density logic. zField-programmable gate arrays (FPGAs) provide more logic and multi-level logic. zApplication-specific integrated circuits (ASICs) are manufactured for a single purpose. 40

41. 8/25/2015 The PC as a platform zAdvantages: yA wide variety of I/O devices yrich and familiar software environment. zDisadvantages: yLarger, more power hungry yrequires a lot of hardware resources; ynot well-adapted to real-time. 41

42. 8/25/2015 Typical PC hardware platform CPU CPU bus memory DMA controller timers bus interface bus interface high-speed bus low-speed bus High-speed device 42

43. 8/25/2015 Typical busses zPCI: standard for high-speed interfacing y33 or 66 MHz. yPCI Express:wide buese with many data and address bits along with multiple control bits. zUSB (Universal Serial Bus), Firewire (IEEE 1394): relatively low-cost serial interface with high speed. 43

44. 8/25/2015 Software elements zIBM PC uses BIOS (Basic I/O System) to implement low-level functions: yboot-up; yminimal device drivers. zBIOS has become a generic term for the lowest-level system software. 44

45. 8/25/2015 Debugging embedded systems zChallenges: ytarget system may be hard to observe; ytarget may be hard to control; ymay be hard to generate realistic inputs; ysetup sequence may be complex. 45

46. 8/25/2015 Host/target design zUse a host system to prepare software for target system: target system host system serial line 46

47. 8/25/2015 Host-based tools zCross compiler:( 交叉编译器 ) ycompiles code on host for target system. zCross debugger: ydisplays target state, allows target system to be controlled. 47

48. 8/25/2015 Software debuggers zBreakpoint zLED. zICE. （电路内部仿真器） zLogic analyzer 48

49. 8/25/2015 Breakpoints zA breakpoint allows the user to stop execution, examine system state, and change state. zReplace the breakpointed instruction with a subroutine call to the monitor program. 49

50. 8/25/2015 ARM breakpoints 0x400 MUL r4,r6,r6 0x404 ADD r2,r2,r4 0x408 ADD r0,r0,#1 0x40c B loop uninstrumented code 0x400 MUL r4,r6,r6 0x404 ADD r2,r2,r4 0x408 ADD r0,r0,#1 0x40c BL bkpoint code with breakpoint 50

51. 8/25/2015 Breakpoint handler actions zSave registers. zAllow user to examine machine. zBefore returning, restore system state. ySafest way to execute the instruction is to replace it and execute in place. yPut another breakpoint after the replaced breakpoint to allow restoring the original breakpoint. 51

52. 8/25/2015 In-circuit emulators (ICE) zA microprocessor in-circuit emulator is a specially-instrumented microprocessor. zAllows you to stop execution, examine CPU state, modify registers. zJTAG 52

53. 8/25/2015 Logic analyzers zA logic analyzer is an array of low-grade oscilloscopes( 示波器 ): 53

54. 8/25/2015 How to exercise code zRun on host system. zRun on target system. zRun in instruction-level simulator. zRun on cycle-accurate simulator. zRun in hardware/software co-simulation environment. 54

55. 8/25/2015 Debugging real-time code zBugs in drivers can cause non- deterministic behavior in the foreground problem. zBugs may be timing-dependent. 55

56. System-level performance analysis zPerformance depends on all the elements of the system: yCPU. yCache. yBus. yMain memory. yI/O device. 8/25/2015 memory CPU cache 56

57. 8/25/2015 Bandwidth as performance zBandwidth applies to several components: yMemory. yBus. yCPU fetches. zDifferent parts of the system run at different clock rates. zDifferent components may have different widths (bus, memory). 57

58. 8/25/2015 Bandwidth and data transfers zVideo frame: 320 x 240 x 3 = 230,400 bytes. yTransfer in 1/30 sec=0.033 sec for a frame.  Transfer 1 byte/  s, 0.23 sec per frame. yToo slow. zIncrease bandwidth: yIncrease bus width. yIncrease bus clock rate. 58

59. Bus bandwidth zT: # bus cycles. zP: time/bus_cycle. zTotal time for transfer: yt = TP. zW:W-wide set of bytes. zD: data payload length. zOverhead: O=O1 + O2 8/25/2015 O1DO2 W T basic (N) = (D+O)N/W 59

60. Bus burst transfer bandwidth zT: # bus cycles. zP: time/bus cycle. zTotal time for transfer: yt = TP. zB: a burst performs B transfers of w bytes. zD: data payload length. zO = O1 + O2. 8/25/2015 BO W T burst (N) = (BD+O)N/(BW) 21 … 60

61. 8/25/2015 Bandwidth problems of memory ----Memory aspect ratios( 长宽比 ) 64 M 16 M 8 M 14 8 61

62. 8/25/2015 Memory access times zMemory component access times comes from chip data sheet. yPage modes allow faster access for successive transfers on same page. zIf data doesn’t fit naturally into physical words: yA = [E*w/W]+1 62

63. Bus performance bottlenecks zTransfer 320 x 240 video frame 30 frames/sec = 6,912,000 bytes/sec. zIs performance bottleneck bus or memory? 8/25/2015 memory CPU 63

64. 8/25/2015 Bus performance bottlenecks, cont’d. zBus: assume 1 MHz bus, D=1, O=3,w=2: yT basic = (1+3)6,912,000/2 = 13,824,000 cycles = 13.82 sec. zMemory: try burst mode B=4, width w=0.5,D=1,O=4,100MHz bus. yT mem = (4*1+4)6,912,000/(4*0.5) = 27,648,000 cycles = 0.2765 sec. 64

65. Performance spreadsheet 8/25/2015 Bus memory Clock1.00E-6Clock1.00E-8 W2W0.5 D1D1 O3O4 B4 N6 912 000N T basic 13,824,000T mem 27,648,000 t13.82T0.2765 65

66. Parallelism zSpeed things up by running several units at once. zDMA provides parallelism if CPU doesn’t need the bus: yDMA + bus. yCPU. 8/25/2015 66

67. summary zBus zI/O devices zDevelopment and debug 67

68. homework 1.4-2, 2. 4-6, 3. 68