1. Harris Corner Detector on FPGA Rohit Banerjee Jared Choi 15-418: Parallel Computer Architecture and Programming

2. Introduction to the problem

3. Corner detection Corner Detection Corners provide a lot of information Spending time to detect corners can significant reduce computation time * Image matching * Motion tracking * Robot Navigation

4. Application Specific Need Pixel Stream Output CORNER DETECTOR Want to be able to process images in real time. Corner detection is very memory intensive. CPU cannot process data fast enough because it had to store data to DRAM first.

5. Exploit arbitrary hardware parallelism to process more within the given time window

6. Harris Detector Basic Idea

7. Hardware Implementation

8. Processing Pipeline

10. Grayscale

11. Processing Pipeline

13. Sobel Filter

14. 2D convolution

15. Convolution Buffer

24. After a while……

25. Convolution Buffer This column is ready to be processed 0 1 N-2 N-1

26. Convolution Buffer 0 1 N-2 N-1

27. Convolution Buffer 0 1 N-2 N-1

28. Processing Pipeline

30. Gaussian Filter

31. Processing Pipeline

33. Harris Response Harris Input ∑Gadxdx ∑Gadydy∑Gadxdy = Sxx Sxy Syy

34. Harris Response

35. Results PlatformExecution Time/ms Naïve Serial Implementation351.20 OpenCV18.12 SystemVerilog(50MHz)1.31

36. Results Platform Speedup of FPGA Implementation Naïve Serial Implementation268.09 OpenCV13.83

37. Results Hardware Approx. Power Consumption/W Intel i3-433042.00 Cyclone IVE FPGA6.30

38. Thank you for your attention