1. AT94 Training 2001Slide 1 AT40K10 AT40K20 AT40K40 AT40K80 5K-10K10K-20K20K-30K40K-50K80K-100K125K-150K 2565761,0242,3044,0966,400 AT40K Family w/ FreeRAM TM PINOUT COMPATIBILITY D DQ CLK RESET Q SET Gates Registers 128192256384512640 I/Os 5Volt/ 3.3Volt Com / Ind Temp PCI-Compliant Specs/Pkgs CLEAR LOAD FreeRAM TM AT40K125 AT40K05 2,0484,6088,19218,43232,76851,200 84 - PLCC 100 - VQFP 144- TQFP 160 - PQFP 208 - PQFP 225 - BGA 240 - PQFP 304 -PQFP 352 - BGA

2. AT94 Training 2001Slide 2 Proven AT40K FPGA Technology SRAM based technology LUT cell based Distributed SRAM blocks FreeRam Tm from 4.6K – 18.4K bits Fully symmetrical architecture Partial/Dynamic reconfiguration Family of AT40K05/10/20/40 in production for more than 3 years Tools/application notes/ IPs available. FPSLIC- Embedded FPGA Core

3. AT94 Training 2001Slide 3 FPGA Core Overview Distributed FPGA RAM I/O Repeaters Core Cells >> Patented RAM can reduce FPGA size requirements by >50% Interface to AVR and SRAM

4. AT94 Training 2001Slide 4 FPGA Cell to Bus Connections Each Cell input can be connected to a local bus Each Cell output can be connected to a local bus 5 Local buses horizontally per sector row 5 local buses vertically per sector column

5. AT94 Training 2001Slide 5 Cell to Cell Direct Connections Each Cell connects to 8 nearest neighbors Each Cell has 4 orthogonal connections Each Cell has 4 diagonal connections

6. AT94 Training 2001Slide 6 X3Y0X3Y0 X2Y0X2Y0 X1Y0X1Y0 X0Y0X0Y0 X3Y1X3Y1 X2Y1X2Y1 X1Y1X1Y1 X0Y1X0Y1 X3Y3X3Y3 X2Y2X2Y2 X1Y2X1Y2 X0Y2X0Y2 X3Y3X3Y3 X2Y3X2Y3 X1Y3X1Y3 X0Y3X0Y3 X3X3 X2X2 X1X1 X0X0 PiPi CiCi C i+1 P i+1 Y0Y0 Y1Y1 Y2Y2 Y3Y3 P7P7 P6P6 P5P5 P4P4 P3P3 P2P2 P1P1 P0P0 + PiPi CiCi XiXi YiYi C i+1 P i+1 Array Multipliers Parallel Multiplier Cell >> Key to High-Performance Processing

7. AT94 Training 2001Slide 7 FPGA Core Cell NWNESESW"1" N SEW 8x1 LUT a0a1a2 out 8x1 LUT a0a1a2 out "1""0" "1" Z CLOCK RESET or SET 01 D Q NWNESESWNESW "1"OE H V "1" XWY Z(L)X(L)W(L)Y(L) V1 H1 V2 H2 V3 H3 V4 H4 V5 H5 XY 1-X 3-W 2-Y 4-Z Cell Inputs Highlighted in italics 5-OE Feedback

8. AT94 Training 2001Slide 8 Sample AT40K Core Cell ‘Modes’ ‘Arithmetic’ Mode ‘Synthesis’ Mode ‘DSP’ Mode ‘Network’ Muxing Mode A B CIN Full Adder/Counter Sum Carry A B CIN Multiplier Cell Carry Product A A B Select Switches B C D Reg 4 LUT 3 LUT PPSI LUT 3 Logic Out Enable OUT 2:1 MUX Random Logic Reg

9. AT94 Training 2001Slide 9 AT40K Key Features DSP Atmel Features: Core cell ‘up-stream’ AND gate give 1 multiplier ‘tile’ per core cell. Diagonal and Orthogonal core cell connection mean no bussing resource consumed to make array multiplier AT40K 4 X 4 array multiplier 16 core cells Xilinx 4K series requires 12 CLBs to create a 4 x 4 array multiplier. Each CLB is equivalent to 2 Atmel core cells which means a Xilinx 4 x 4 array multiplier is equivalent to 24 Atmel core cells. Xilinx does not have diagonal direct connects so they also consume a large number of bus resources to do multiplier. CLB cell Atmel Diagonal direct connection Xilinx need two buses to make a Diagonal

10. AT94 Training 2001Slide 10 FPGA SRAM 32 X 4 Ram in corner of each sector Ram can be sync or async Ram can be single or dual ported Ram can be reset via configuration Ram can operate at 100MHz Data and address come from local and express bus connections 32x4 RAM DinDout WAddrRAddr WE OE Dedicated SRAM routing resource

11. AT94 Training 2001Slide 11 AT40K Key Features FreeRAM Atmel Features: Distributed SRAM “FreeRAM” Fast 10ns access time Fully Programmable Single or Dual port Synch or Async Using RAM does not use core cells Xilinx 4K series has 16 x 1 Dual port Ram in each CLB 32 x 4 Dual port RAM is 8 CLBs and each Xilinx CLB is 2 X an Atmel core cell. A Xilinx 32 X 4 Dual port RAM consumes the equivalent of 16 Atmel core cells !!!! With AT40K the RAM is FREE 32x 4 bits of Dual port RAM

12. AT94 Training 2001Slide 12

13. AT94 Training 2001Slide 13 AT40K Clocking Scheme Individual Clock per sector column Clock and Clock BAR at sector boundary Column Clock can be any one of 8 Global clocks Clock from Column Clock or Express Bus 4 Fast Clocks (2 per side for PCI spec) Low power tie-off

14. AT94 Training 2001Slide 14 AT40K Reset Scheme Individual reset per Sector column Reset and Reset BAR Any device pin can be designated as reset Reset from Global Reset or Express Bus Each D Flip-Flop can be Set or Reset

15. AT94 Training 2001Slide 15 FPGA Primary I/O I/O interfaces to core cell I/O connects into repeaters on row above and row below Programmable input delay CMOS/TTL input levels Pull-up or pull-down resistor Open source/drain output System friendly bus keeper >> Supports Pin-Locking!

16. AT94 Training 2001Slide 16 cell P S P P P P P P P P P P P P S S S S S S S S AT40K Key Features Pin Locking Unique I/O bus connections mean that pin locking problems are virtually eliminated 1 Primary I/O connects to 12 core cells & 1 Secondary I/O connects to 8 core cells AT40K ‘Lock-it and Leave-it’ tm I/O structure

17. AT94 Training 2001Slide 17 FPGA Designs IDS supports Schematic, VHDL or Verilog Design Entry It generates a BST file for programming the Configurator AT40K FPGA AT17 Figaro IDS FPGA Development Tools

18. AT94 Training 2001Slide 18 HDLPlanner™ Technology independent design entry Enhances design re-use Shorter design cycle Supports Verilog & VHDL Syntax correct templates Support for macro generators Context highlighting Seamless interface to synthesis Integrate user defined components Knowledge archival FPGA HDLPlanner ™

19. AT94 Training 2001Slide 19 Push Button IP - Macro Generators Macro Generators Hard or Soft Layouts Parameterizable Auto HDL generation Auto Schematic Generation Auto Simulation Model Power Calculation Area Calculation Post Layout Performance Architecture Optimized Open development lang.. Auto insertion of pipelining Supports Logic & Memory

20. AT94 Training 2001Slide 20 Exemplar Leonardo Spectrum  HDL Synthesis Easy to use Fast RTL Optimization Produces the best results Integrated RTL to P&R

21. AT94 Training 2001Slide 21 ModelSim  HDLSimulation Committed to HDL Simulation Leadership Quick Compilation Fast Simulation Ease-of-Use Full debug at any level

22. AT94 Training 2001Slide 22 FPSLIC-FPGA Development Software FPGA Development Tools Push Button 85%+ APR XNF/EDF/WIR Import Hierarchy Browser Architecture Mapping Multi-Chip Partitioning Floor planner Bitstream Utilities Incremental Design Change Export VHDL/Verilog netlists Back Annotation support Extensive interactive help.

23. AT94 Training 2001Slide 23 FPSLIC-FPGA Development Software FPGA Development Tools User Library Management Enhances Design re-use Interactive Layout Editor Timing Driven Design Graphical Constraint Entry Multi Cycle Clk Constraint Async. Path Delay Constraint Static Timing Analysis Interactive Timing Analysis