1. Self-Biased, High-Bandwidth, Low- Jitter 1-to-4096 Multiplier Clock Generator PLL Based on a presentation by: John G. Maneatis 1, Jaeha Kim 1, Iain McClatchie 1, Jay Maxey 2, Manjusha Shankaradas 2 True Circuits, Los Altos, CA 1 Texas Instruments, Dallas, TX 2 PDF file of JSSC paper linked at class web page.

2. 2 Clock Generator PLLs for ASICs  Most ASICs PLLs for clock generation, but …  Use different frequencies and multiplication

3. 3 Optimal PLL Design  For each F OUT and N, one must adjust loop parameters for both minimum jitter and stability  For clock generators (track input clocks) (  REF = 2  ·F OUT /N)  Loop bandwidth :  N ~  REF /20  Damping ratio :  ~ 1  Third-order pole :  C ~  REF /2  Circuit parameters (e.g. I CH, R) must vary with F OUT and N!

4. 4 Addressing Diverse Specifications  Designing a different PLL for each ASIC  Easier to meet the specification, but …  Verifying all designs is difficult and costly  Our Goal: One PLL design for all ASICs  Only one design needs verification, but …  Loop parameters must adjust automatically to satisfy wide range of F OUT and N

5. 5 Challenges  Self-biased PLLs [Maneatis ‘96] adjust for F OUT  Achieve fixed  N /  REF and  indep. of PVT  But, Self-Biased PLLs do NOT adjust for N   N /  REF and  vary with N (want fixed)   C /  REF varies with N (want fixed)  This talk extends Self-Biased PLLs for wide ranges of N with a new loop filter network

6. 6 Outline  Introduction  Review of Self-Biased PLLs  Pattern Jitter Issues  Loop Filter Architecture  Implementation of Key Circuits  Measured Results  Conclusions

7. 7 Second-Order PLLs

8. 8 Oscillation frequency is supposed to be controlled by V CTL, that is by I CH /CS + I CH *R. In Ring Oscillators, frequency is more easily controlled by current, through tail biasing voltage.  want tail current to have two components: ICH/CS + ICH*R.

9. 9 Self-Biased PLLs V BN biases the tail current in Ring Oscillator buffer stages. So want I D to have components:

10. 10 Self-Biased PLLs Op Amp adjust V BN so that NMOST ID matches currents in 1/gm and that from top charge pump. Notice: V CTL = V DD – I CH / sC 1 d I D = (V DD – V CTL )gm + I CH-ff = I CH (1/sC 1 + 1) Hence V BN will generate I-tail proportional to I CH (1/sC 1 + 1)

11. 11 Maneatis self bias generator From 1996 Maneatis paper, which is very widely reference. PDF file linked at web page.

12. 12 Self-Biased PLLs  With Self-Biased PLLs   N /  REF and  are constant with F OUT, BUT not with N

13. 13 Pattern Jitter / Spurious Noise  Phase corrections every rising reference edge can cause disruptions to nearby output cycles  Periodic noise pattern repeats every ref. cycle or N output cycles  Typical causes  Charge pump imbalances or leakage  Jitter in reference clock (aperiodic result)

14. 14 Shunt Capacitor  Use third-order pole to extend disturbance with reduced amplitude over many output cycles  Problem with varying N using fixed capacitor  Extended number of cycles NOT function of N  Too few for large N  Pattern jitter  Too many for small N  Instability

15. 15 Proposed Loop Filter  Use switched capacitor filter network to  Output scaled amplitude error signal with N output cycle duration [Maxim ’01]  Want a simple solution using this approach that is compatible with Self-Biased PLLs

16. 16 Original Filter Network  Only need to filter feed-forward path

17. 17 Sampled Feed-Forward Network  Sample phase error and generate proportional current that is held constant for N·T OUT  Sampled error is reset at end of ref. cycle  Need V RST = V CTL as zero bias level

18. 18 Complete Filter Network  Reset C 2 to V CTL directly  Eliminates C 1 charge pump  Equivalent feed-forward control gain Q O ~ N · Q I

19. 19 Loop Dynamics  With this new loop filter network we achieve  Need to keep  N /  REF and  constant with N  Just scale charge pump current with 1/N (=x)  More detailed analysis will show  Both are independent of F OUT, N, and PVT!

20. 20 Complete Self-Biased CGPLL

21. 21 Self-Biased Filter Network

22. 22 Filter Network Reset Switches  Can switch to V CTL independent of voltage level

23. 23 Filter Network Reset Switches When un-selected, sel = 0, sel_B = 1 (VDD). V_B = VDD, V_D = VDD + V_CTL, V_A = 0, V_C = V_BR = V_CTL. V_CA charged to V_CTL A B C D

24. 24 Filter Network Reset Switches When selected, sel_B = 0, sel = 1 (VDD). V_A = VDD, V_C = VDD + V_CTL, V_B = 0, V_D = V_BR. V_DB charged to V_BR or V_CTL A B C D

25. 25 Inverse-Linear Current Mirror  Need to generate I CH = I D / N  Use switches to adjust device size on input side  For N=1~4096, need 12 binary weighted legs  Need size range of 2048:1  Too much area!

26. 26 Multi-Stage Linear CM  Solution to size problem with LINEAR control  Use multiple device groups operating at different but ratioed current densities  Can have large ranges using small devices

27. 27 Multi-Stage Inverse-Linear CM  Just diode connect multi-stage linear current source and use as input side of current mirror  Can output gate bias of any device group  Stable as long as gain blocks reduce currents

28. 28 Complete Current Mirror

29. 29 Voltage-Controlled Oscillator

30. 30 Buffer Tail Node Matching

31. 31 Modified VCO

32. 32 Static Supply Sensitivity 32

33. 33 PLL Implementation Process Technology 0.13  m N-well CMOS Nominal Supply Voltage1.5V (designed for 1.2V) Total Occupied Area0.38 x 0.48mm 2 VCO Frequency Range30 ~ 650 MHz Multiplication Factor RangeN = 1 ~ 4096 Power Dissipation7mW @ 240 MHz, 1.5V

34. 34 Measured Jitter vs N (240MHz)

35. 35 PLL Jitter Measurement Summary

36. 36 Conclusions  Proposed PLL achieves wide N and F OUT range  PLL is self-biased with constant loop dynamics (  N /  REF,  ), independent of N, F OUT, and PVT  Sampled feed-forward network suppresses pattern jitter with effective  C that tracks  REF  Achieves relatively constant period jitter of less than 1.7% as N is scaled from 1 to 4096

37. 37 References  J. Maneatis et al., “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 424–425.  J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723– 1732, Nov. 1996.  A. Maxim et al., “A low-jitter 125–1250 MHz process-independent 0.18 m CMOS PLL based on a sample-reset loop filter,” in IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 394–395.  T. C. Lee and B. Razavi, “A stabilization technique for phase-locked frequency synthesizers,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 39–42.  J. Maneatis and M. Horowitz, “Precise delay generation using coupled oscillators,” IEEE J. Solid-State Circuits, vol. 28, pp. 1273–1282, Dec. 1993.