1. 14-5 January 2006 Luciano Musa / CERN – PH / ED General Purpose Charge Readout Chip Nikhef, 4-5 January 2006 Outline  Motivations and specifications  Architecture & building blocks  Programmable Charge Amplifier  Time-interleaved Multi-Channel A/D Converter  Digital filtering and Signal Feature Extraction  Project Milestones

2. 24-5 January 2006 Luciano Musa / CERN – PH / ED Motivations & Specifications 1/2 Requirements of the front-end and readout electronics for High Energy Physics Experiments: low power, high speed, high density, low mass, radiation tolerance These requirements can only be met by highly integrated systems implemented with very deep submicron CMOS technologies. The volumes of ICs required for a typical HEP detector remain low <1Mch Non Recursive Engineering (NRE) costs are more and more dominant for high energy physics. Development of standard chips capable of handling a wide range of high energy physics applications, in order to warrant the NRE expenditure. Likely this polyvalence will be obtained through an increased level of programmability.

3. 34-5 January 2006 Luciano Musa / CERN – PH / ED A general purpose charge readout chip number of readout channels: 32 or 64 programmable charge amplifier: sensitive to a charge in the range: ~10 2 - ~10 7 electrons Input capacitance: 0.1pF to 10pF high-speed high-resolution A/D converter: sampling rate in the range 40MHz - 160MHz; programmable digital filter for noise reduction and signal interpolation; a signal processor for the extraction and compression of the signal information (charge and time of occurrence). Motivations & Specifications 2/2

4. 44-5 January 2006 Luciano Musa / CERN – PH / ED Charge Readout Chip Block Diagram 32 / 64 Channel Charge Amplifier Anti- Aliasing Filter ADC Signal Processor Data Compression Multi-Acq Memory Hit Finder Feature Extaction Histogrammer Charge Amplifier Anti- Aliasing Filter ADC Signal Processor Data Compression Multi-Acq Memory Charge Amplifier Anti- Aliasing Filter ADC Signal Processor Data Compression Multi-Acq Memory INTERFACEINTERFACE Maximize S/N reduce quantization error reduce signal bandwidth Correct for crosstalk and common mode noise Optimum pulse shaping for extraction of pulse features

5. 54-5 January 2006 Luciano Musa / CERN – PH / ED Milestone I (Q4 2006) ⇒ Programmable Charge Amplifier (prototype) –16 channel charge amplifier + anti-aliasing filter. Milestone II (Q2 2007) ⇒ 10-bit multi-rate ADC (prototype) –4-channel 10-bit 40-MHz ADC. The circuit can be operated as a 4-channel 40- MHz ADC or single-channel 160-MHz ADC. Milestone III (Q2 2008) ⇒ Charge Readout Chip (prototype) –This circuit incorporates 32 (or 64) channels. Milestone IV (Q2 2009) ⇒ Charge Readout Chip (final version) Project Milestones

6. 64-5 January 2006 Luciano Musa / CERN – PH / ED Phase DetectorCharge Pump Voltage Controlled Delay Line up down Vctrl Ref. Clock (40 MHz) C B A D A/D Multi-Channel Time-Interleaved A/D Converter A B A C A C D Upgrade of ALTRO ADC 4-Channel 40-MHZ ADC A B C D 2-Channel 80-MHZ ADC C A A C 1-Channel 160-MHZ ADC A A A A aa bb cc dd CLK aa bb cc dd aa bb cc dd

7. 74-5 January 2006 Luciano Musa / CERN – PH / ED Low-noise Amplifier (CMOS 0.13  m) Increased gm Better ENC (Should ideally improve by ca. 20% per CMOS Generation)  Low Supply Voltage limits SNR Smaller Dynamic Range Rail to Rail Design Invest Power to improve SNR Big Capacitors Design Shaping Circuit for Low Noise  Reduced Gate Oxide Thickness Gate Tunneling Current Radiation Tolerance  Short Channel Effects Hot Carrier Stress – Reliability, Noise Velocity Saturation

8. 84-5 January 2006 Luciano Musa / CERN – PH / ED - I det Rf (M  ) Cf Rf/20 Cf *20 - Z(s) -20 I det V bias Vgs 4 th Order Low Pass Filter The Resistance of the Feedback Element is a function of its Gate to source Voltage  Vgs is the same for both Transistors  corresponding resistances track each other  The CSA’s input dc level is equal to its output dc level  The Current Gain is -20 Architecture: CSA + Semi Gaussian Shaper Low-noise Amplifier (CMOS 0.13  m)

9. 94-5 January 2006 Luciano Musa / CERN – PH / ED ENC ca. 300 electrons rms (@12pF C in ) Peaking Time 100ns 4 th Order Semi Gaussian Shaper 9mW Power Consumption Charge Range 0-160fC (negative polarity) Output Stage: 30pF driving capability Differential Output Feedback Resistance of CSA ca. 10 MOhm Low-noise Amplifier (CMOS 0.13  m) Specifications of the first prototype

10. 104-5 January 2006 Luciano Musa / CERN – PH / ED The area is dominated by the size of the Capacitors  IBM CMOS 8RF, 0.13 um  CSA Area = 50um X 500um = 0.025mm 2  Total Area per Channel = 0.075mm 2  16-channel chip  3mm 2 Low-noise Amplifier (CMOS 0.13  m) Circuit Layout Submitted in December ‘05

11. 114-5 January 2006 Luciano Musa / CERN – PH / ED Mapping the s-Plane into the z-Plane Re Im z-plane 0 1 Re Im s-plane 0  jj Sampled time functions that exponentially decrease with increasing time Sampled time functions that exponentially increase with increasing time Oscillating sampled time functions Z=1, constant or increasing functions depending on the multiplicity of the pole

12. 124-5 January 2006 Luciano Musa / CERN – PH / ED Zero-Pole Locations Re Im z-plane Real Positive Zeros and Poles 16-bit coefficient coding 0 1 Re Im z-plane 0 1 ALTRO Filter New Filter Complex Zeros and Poles 18-bit coefficient coding

13. 134-5 January 2006 Luciano Musa / CERN – PH / ED The pulse representation in the sample space S1(  S2 (  ) S3 (  ) Find the pulse features, Amp = F(S1,S2,…) and time = T(S1,S2,..), as quasi-invariants in the sample space Recovery of signal parameters 2/2 Extraction of the pulse features (amplitude and time) V. Buzuloiu et al. A =  a i (  j ) S i