1. August 2008 Hi-Rel Operations 2010

2. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. National – A Global Company Taiwan China India Finland Germany South Portland, ME Japan Malaysia Netherlands Scotland Santa Clara, CA Estonia Korea –Santa Clara, Ca USA –Melaka, Malaysia –South Portland, Maine USA –Greenock, Scotland Regional Business Divisions Wafer Fabs Assembly Plants –Americas –Europe – United States (15) – Scotland – The Netherlands – Germany – Italy – India World Headquarters –Santa Clara, California, US Design Centers – China – Taiwan – Japan – Finland – Estonia – Korea –Japan –Asia Pacific Italy

3. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. World-Class Manufacturing Our Strategic Asset Greenock, Scotland – 6in –Leading-edge analog Bipolar, BiCmos + Dmos, CMOS processes South Portland, Maine – 8in –Advanced CMOS / BiCMOS (SiGe and SOI) processes –Running advanced analog –US Secure Foundry Santa Clara, USA and Melaka, Malaysia –Custom Hermetic Package Design –Test & Assembly

4. August 2008 Hi Rel Operations

5. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. National Semiconductor – A Rich Space Analog Portfolio Analog Building Blocks QMLV Qualified Products State of the art radiation tolerant process technology (ELDRS Free) State of the art radiation tolerant process technology (ELDRS Free) Industry leading hermetic package technology Industry leading hermetic package technology Renewed focus on Technology Driven Analog Solution Renewed focus on Technology Driven Analog Solution Radiation Testing: SEL, SEU & TID Reports Radiation Testing: SEL, SEU & TID Reports 30+ Years in the Space Market

6. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Hi-Rel Operations Private Customer Portal Released Product Information –QML Datasheets –Radiation Reports TID SEL SEU SET Products in Development –Preliminary Datasheets –Preliminary Radiation Reports Hi-Rel Contacts www.national.com/portal/hirel_customer –Or go to www.national.com/space, scroll down to “ Private Customer Portal ” linkwww.national.com/space

7. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Hi-Rel Operations Customer Support and Documentation Ceramic Eval Boards Radiation Reports TID SEU/SET SEL Customer Communications –Quarterly News Letter –Customer Portals –Hi-Rel Web Site www.national.com/space ADC08D1520CVAL ADC14155HCVAL ADC14155LCVAL ADC10D1000CVAL LM98640CVAL

8. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Die Products at National WAFER –Whole wafers in vials DICED –Waffle Pack –GEL-PAK ® –Tape on Reel –Wafer on film frame Die Products contact –See web site for information Web –www.national.com/diewww.national.com/die

9. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Hi-Rel Focused Satellite Strategy ELDRSAOCSCommunicationSpace ImagingPower Work with our customers to help solve system challenges by developing leading edge Analog Solutions enabling innovative and successful missions. 1.Enhanced Heritage Products 2.Aggressively pursue the satellite market with high performance fully QMLV qualified analog products Wide Band Narrow Band

10. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. What is ELDRS and Why is It Important? Many bipolar linear circuits are used in space systems and many suffer from ELDRS System performance may be degraded by ELDRS It is hard to identify system malfunctions related to ELDRS – “Failures” are usually parametric and not functional – Design margins are often high – Circuits are often not “suspect” if they passed ground test at HDR ELDRS has been demonstrated in space (See papers from NSREC & RADECS) Enhanced Low Dose Rate Sensitivity: An increase degradation in electrical performance between low dose rate and high dose rate. High and Low Dose Rate Improvements - legacy Portfolio

11. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Comparison Space to Ground Testing

12. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Comparison Space to Ground Testing

13. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. We test them so you don’t have to! Every wafer tested and qualified at low dose rates –per Mil-Std-883 method 1019 condition A&D –Low dose rate of 10 mrad/s (36 rad/hr) –Biased and unbiased DSCC unique low dose rate certified part numbers ELDRS Free Products LM111 LM117 LM124 LM136-2.5 LM139 LM158 LM193 LM7171 LM119 LM2941 LMP2012 Low Dose Rate Qualified LM117HV Products in Qualification LM101 LM137 LM113 LM2940 ELDRS-Free Products! ELDRS-Free LM139 Also available in die form

14. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Radiation process developed to improve total dose performance –LM13710krad30krad –LF41110krad50krad –LM10110krad50krad –LM11110krad50krad –LM13610krad100krad –LM15810krad100krad –LM12410krad100krad –LM13910krad100krad –LM11710krad100krad –LM117HV3krad100krad –LP295310kradIn Progress High Dose Rate Improvements - on Legacy Products Continue to work on radiation performance for existing devices BeforeToday

15. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Hi-Rel Focused New Product Development ApplicationsAOCSPowerCommunication Space Imaging System Function Maintain or Change Orbit Payload & Bus Backbone of Communications Market Integral in National Security and Tracking System Requirements Lower Power, Increase Precision Higher Efficiency, <1.2V, Faster Response Time, High Currents Higher Bandwidth, Lower Noise Power Ratio, Lower Power Lower Power, Higher Resolution, More Integration Products Developed 1 MSPS ADC & DACs Precision Amps LDOS High Speed & Giga Sample ADCs Low Power Analog Front Ends

16. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC128S102WGRQV - QMLV Available today! 8-Channel, 12-Bit, 50 KSPS to 1MSPS, General Purpose ADC –Only 2.3mW of Power 0.06 uW in Power Down –Eight Input Channels –DNL – -0.2 to +0.4 LSB typical –INL – +/- 0.4 LSB typical –Split Supplies V A 2.7V to 5.25V V D 2.7V to V A –SPI Digital Output –16ld Gull Wing Ceramic Cerpac –Space Level Version TID of 100 krad(Si) Single Event Latchup > 120 MeV –Order as 5962R0722701VZA 50 KSPS 1 MSPS

17. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC128S102WGRQV Specifications Std Ceramic package WG16A 8 Channels in only 16 pins –Reduces board space and weight –Reduces PCB traces and cabling

18. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. DAC121S101WGRQV - QMLV Available Now! 12-Bit Micro Power General Purpose DAC with Rail-to-Rail Output 0101001101001 1001011001101 0101001101001 1001011001101 0101001101001 1001011001101 0101001101001 1001011001101 Vcc Gnd Din Sclk Snyc Vout –Only 0.64mW of Power 0.14 uW in Power Down –Supply range of +2.7V to +5.5V –Guaranteed Monotonic –DNL +0.25/-0.15 LSB –3-wire 20MHz SPI Digital Interface –Settling Time 12μS –Hermetic 10ld Gull Wing Ceramic Cerpac –Space Level Version TID of 100 krad(Si) Single Event Latchup > 120 MeV –Order as 5962R0722601VZA

19. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. DAC121S101WGRQV Specifications Std Ceramic package WG10A Serial interface –Allows for small 10 pin package –Reduces package footprint and weight –Reduces PCB traces and cabling

20. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. LMP2012WGLQMLV - Dual Channel, High Precision, Rail- to-Rail Output Op Amp –Very Low TCV OS – 0.015uV/°C –Low Input offset voltage of 60 μV over time and temperature. –No 1/f noise - input-referred voltage noise of 35 nV/ Hz –Low supply current – 920uA –Wide gain bandwidth – 3MHz –2.7 to 5.0V supply voltage range –High CMRR – 130 dB –High PSRR – 120 dB –Hermetic 10-pin ceramic gullwing flat package –Space Level version TID of 50 krad(Si) ELDRS qualified to 50 krad(Si) Low SET Cross-Section –Order as 5962L062061VZA QMLV Available!

21. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. No 1/f Noise Input-Referred Voltage Noise of 35 nV/ Hz

22. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Offset Voltage - Over Supply and Temperature

23. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. SET Results Low Sensitivity to SET event with the LET threshold being close to 4meV/cm 2 /mg The longest lasting transit was ~1.5μs

24. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. LM2941QML ELDRs Free 1A LDO Features –1A Adjustable Regulator –Adjustable Output Voltage 5V-20V –Input Voltage up to 26V –Input protection up to -15V –Drop Out Voltage 0.5V –Quiescent Current 10mA –On / Off Pin –Internal short circuit current protection –ELDRs Free up to 100krad/si Available!

25. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC14155 - Space Qualified Available Today! 14-bit 155 MSPS ADC –Input bandwidth of 1.1GHz –11.3 ENOBs at f in =70 MHz, 11 ENOBs at f in =169MHz –SNR of 70.1 dB at f in =70 MHz, 68.5 dB at f in =169MHz –SFDR of 82.3 dB at f in =70 MHz, 80.5 dB at f in =169MHz –Power Consumption of 967mW at 155 MSPS –Guaranteed no missing codes –Dual 1.8V and 3.3V operation –In 48 pin Hermetic Ceramic Quad Flat Pack –Space Level Version TID of 100 krad(Si) Single Event Latchup > 120 MeV PLL VCO BPF LMH6517 ADC14155 BPF LMH6517 ADC14155 RF

26. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. National vs. Competition

27. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC14155 ENOB vs. Temperature

28. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC14155 SFDR vs. Temperature

29. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC14155 SINAD vs. Temperature

30. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC14155 Power vs. Sampling Rate

31. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Dual Channel 8-Bit 1.5 GSPS ADC, Single 8-bit 3 GSPS ADC ADC08D1520WGFQV - QMLV Available! –Max sampling frequency 1.7GSPS –Inputs may be interleaved to obtain a 3GSPS single ADC –Input bandwidth of 2 GHz –7.2 ENOBs out to Nyquist –Lowest Power in the industry at 1 W per channel at 1.5 GSPS from single 1.9V supply –Very low cross-talk (-66 dB @ 1160 MHz) –Low-noise deMUX’d LVDS outputs –Guaranteed no missing codes –In 128 pin Hermetic Ceramic Quad Flat Pack –Space Level Version TID of 300 krad(Si) Single Event Latchup > 120 Mev –Order as 5962F0721401VZC

32. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. 128-Lead Ceramic Quad (Gold Lead Finish) NS Package Number EL128A

33. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC08D1520WGFQV ENOB vs. Clock Freq, Input Frequency 248.47MHz versus Temperature. Bench @ Room and Hot Hot Room

34. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Bench 150°C Temperature Set-up. Thermo-stream “elephant” Temperature forcing through a copper plated funnel directly onto the surface of the socket heat sink. An LM95221 is used to monitor the actual junction temperature. With the ADC10D1000 I and Q Channels in power down mode the junction temperature is equal to 26’C. Once power is enabled the junctions settle around 75’C. The elephant is set at 150’C to get the junctions around 145’C. Some heat is lost due to the open test environment.

35. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Bench FFT, Sample Rate = 1500Mhz, Input 397.47MHz I Channel

36. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Bench FFT, Sample Rate = 1500Mhz, Input 797.47MHz I Channel

37. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Bench FFT, Sample Rate = 1500Mhz, Input 997.47MHz I Channel

38. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Bench FFT, Sample Rate = 1500Mhz, Input 1597.47MHz I Channel

39. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. 1.0 GSPS Clk +1.0dBm, 247.97Mhz +3.6dBm I/F Non-SPI Mode, FS=1(870mV pk-pk) Note: The Input Amplitude is held constant over the temperature range. Key Points: Calibration was performed only upon Pwr up.Then Cal was performed again after last temperature sweep. Key Points: Calibration was performed only upon Pwr up. Then Cal was performed again after last temperature sweep. Calibration performed at every Temperature Change. Dynamic vs. Temperature ADC08D1520WGFQV with and without Cal

40. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. GiG Evaluation System - Enable complete system demo for customers NSC’s ceramic evaluation board interfaces to a PC through the USB interface. National uses a Xilinx Virtex-4 processor for the data capture. National also supplies the wavevision software for data analysis.

41. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC10D1000QML - Space Qualified Available Today! Dual Channel 10-Bit 1GSPS ADC, Single 10-bit 2 GSPS ADC –Full Power Bandwidth of 2.8 GHz –9.0 ENOBs @ Fin 249MHz Fs – 1.0GHz 8.9 ENOBs @ Fin 498MHz Fs – 1.0GHz –56.1dBc SNR @ Fin 249HMz Fs- 1.0GHz 56.8dBc SNR @ Fin 498HMz Fs- 1.0GHz –62.1dBc SFDR @ Fin 249MHz Fs – 1.0GHz 62dBc SFDR @ Fin 498MHz Fs – 1.0GHz –Lowest Power in the industry at 1.45 W per channel at 1GSPS from single 1.9V supply –Inputs may be interleaved to obtain a 2 GSPS single ADC –Very low cross-talk (-61 dB @ 497 MHz) –Low-noise deMUX’d LVDS outputs –Guaranteed no missing codes –In 376 pin Hermetic Ceramic Column Grid Array Package –Space Level Version TID of 100 krad(Si) Single Event Latchup > 120 MeV

42. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. National vs. Competition

43. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Simplified Functional Block Diagram

44. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ENOB vs. Fin I Chan, Ceramic Package @ room, Fclk = 1 GHz QChan, Ceramic Package @ room Fclk = 1 GHz

45. August 2008 I and Q Channel (dBc). I Chan, Ceramic Package @ room Fclk = 1 GHz QChan, Ceramic Package @ room Fclk = 1 GHz SFDR vs. Fin

46. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. NPR vs. Notch Width The NPR was measured at each notch width and the average is shown. At f c,notch = 320MHz, f=250MHz is never included for all notch widths. The measurement stabilizes after about 4%, so a 5% notch width (25MHz, ~750 bins) was chosen for most measurements. After 10%, the NPR begins to degrade.

47. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC10D1000QML Power Power vs Clock Frequency @ Room 1.1 1.4 1.3 1.2 1.5 1.6 1.9 1.8 1.7 Sample Rate (MSPS) Power/Channel (W) ADC10D1000QML

48. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC10D1000QML ENOB vs. f CLK I Channel, LFS = LowI Channel, LFS = High Writing the LFS bit High improves performance at f CLK = 100 MHz. LFS doubles the charge pump frequency improving performance with low f CLK.

49. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC10D1000QML Auto-Sync Feature The ADC10D1000QML has an auto-sync mode for continuous synchronization of an arbitrary number of ADCs in a system A Master-Slave configuration for the subdivision of the converter clock, CLK, to the slower DCLK output is used D1 D2 DCLK CLK V IN T DCLK = 4 x T CLK T CLK ADC #4 RCLK_IN RCLK1RCLK2 AutoSync D1 D2 DCLK CLK V IN ADC #2 RCLK_IN RCLK1RCLK2 AutoSync to ADC #5 to ADC #8to ADC #9 from ADC #1 (Master)

50. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. 376 Column Grid Array Package

51. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. 376 Column Grid Array Package

52. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Columns from 6Sigma Column Core Material: 80Pb/20Sn Column Diameter: 20mils Column Height: 87mils Column Core wrapped with Copper Ribbon and eutectic solder coating of 37Pb/63Sn Copper Ribbon

53. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. National’s 376 Column Grid Array - Temperature Cycle Board Experiment between standard 80Pb/20Sn Copper Ribbon Columns Daisy Chain Test Chip 10Min Dwell 36°C/Min 125°C -55°C Time 1.5min11.5min 13min 0°C 16.5min26.5min 30min

54. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC10D1000 Reinforced Copper Columns after 3000cycles 3000 cycles 80Pb/20Sn

55. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. ADC10D1000 SEE Testing Results No SEL up to 120MeV No SEFI up to 120MeV SEU for DCLK –Outage Time: 0.02ps/month –Clock Upsets: 2.2X10-5 events/month –Longest Event: typically 1 clock cycle SEU Code Error Rate –Outage Time: 0.1ns/ch/month –Data Upsets: 1.8X10-3 events/ch/month –Longest Event: 55ns

56. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Weibull Plots for DCLK

57. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. Weibull Plot for Code Error / Channel

58. August 2008 NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL © 2008 National Semiconductor Corporation. All Rights Reserved. 58